ECEstream: Digital Electronics

Shift Register Counters

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Two of the most common types of shift register counters are introduced here: the Ring counter and the Johnson counter. They are basically shift registers with the serial outputs connected back to the serial inputs in order to produce particular sequences. These registers are classified as counters because they exhibit a specified sequence of states.</div>
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<b><span style="color: #3d85c6;">Ring Counters</span></b></div>
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A ring counter is basically a circulating shift register in which the output of the most significant stage is fed back to the input of the least significant stage. The following is a 4-bit ring counter constructed from D flip-flops. The output of each stage is shifted into the next stage on the positive edge of a clock pulse. If the CLEAR signal is high, all the flip-flops except the first one FF0 are reset to 0. FF0 is preset to 1 instead.<br />
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<img alt="Ring Counter" border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEh_-wgqdGyrqAWwNVtArPuDOzN5sPzehSflti5C2RlU7CVsCEQBKCB7GF7AhoTlecOOVizvGPuoUvdli5PqbHh7-ABYkTEWGd-jN-zQSpj4RgzO70GF5B4D7026B6ryHaTBcumh5qLao-g_/s1600/Ring+Counter1.JPG" title="Ring Counter" /></div>
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Since the count sequence has 4 distinct states, the counter can be considered as a mod-4 counter. Only 4 of the maximum 16 states are used, making ring counters very inefficient in terms of state usage. But the major advantage of a ring counter over a binary counter is that it is self-decoding. No extra decoding circuit is needed to determine what state the counter is in.</div>
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<img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjPe1g8zv8qL6MOn8Is7P4YR_8b3vYQmgKp0bFhG_NaWKqw2LR9-y3tz-qN5e59zZMO7-Rwsu3GtxmAWvyOwM-65U4WUeKbsZQtsLQZsQlw6EBGv8K6tCUAw4wePY2oeHRcenWOLRTv319z/s1600/Ring.JPG" /></div>
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<span style="color: #3d85c6;"><b>Johnson Counters</b></span></div>
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Johnson counters are a variation of standard ring counters, with the inverted output of the last stage fed back to the input of the first stage. They are also known as twisted ring counters. An n-stage Johnson counter yields a count sequence of length 2n, so it may be considered to be a mod-2n counter. The circuit below shows a 4-bit Johnson counter. The state sequence for the counter is given in the table.<br />
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<img alt="Johnson Counter" border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgd3OtfRjuuW-MQLK326Hk7nydQzgsMD06sIgsk3WOEvqzUyUWsaTgjyVTNWUjjltJ7FHNYdNTdtoDcuqDXWHp9gZuSEk8VgICabqMmdiytVh1Vd3ntBVlbEg5AhTePRi4MSa3E0t1kt8X8/s1600/Johnson+Counter.JPG" title="Johnson Counter" /></div>
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Again, the apparent disadvantage of this counter is that the maximum available states are not fully utilized. Only eight of the sixteen states are being used.</div>
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Beware that for both the Ring and the Johnson counter must initially be forced into a valid state in the count sequence because they operate on a subset of the available number of states. Otherwise, the ideal sequence will not be followed.</div>
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Shift Register Counters

Two of the most common types of shift register counters are introduced here: the Ring counter and the Johnson counter. They are basically ...

Shift Registers

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The binary data in a register can be moved within the register from one flip-flop to the other or outside it with application of clock pulses.</div>
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The registers such that allow such data transfers are called as shift registers.</div>
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Shift registers are used for data storage, data transfer and certain arithmetic and logic operations.</div>
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<b>Storage Capacity:</b> The storage capacity of a register is the total number of bits (1 or 0) of digital data it can retain. Each stage (flip flop) in a shift register represents one bit of storage capacity. Therefore the number of stages in a register determines its storage capacity.<br />
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<b>Modes of operation of a shift register:</b></div>
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<li>Serial input serial output</li>
<li>Serial input parallel output</li>
<li>Parallel in serial out</li>
<li>Parallel in parallel out</li>
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<b><span style="color: #3d85c6;">Serial Input Serial Output (Shift Left Mode):</span></b></div>
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The serial in/serial out shift register accepts data serially – that is, one bit at a time on a single line. It produces the stored information on its output also in serial form.</div>
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<b>Basic four-bit shift register:</b></div>
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A basic four-bit shift register can be constructed using four D flip-flops, as shown in Figure 1.<br />
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<img alt="Serial Input Serial Output Shift Register" border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjnDymhya_mej5XQ-j18uvpFbtz79THo-JdJOW240cqXvnjlkjGK2t8Tp75GQXN0ylJtlQkDAp3OVTGLDkpoNeF-KH6qkzvF4fwsZqnO2PcLdV84fdWHDb547J3Bn-NJibi-Ey84Oa7jOZQ/s1600/SISO.JPG" title="Serial Input Serial Output Shift Register" /></div>
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<b>Figure 1</b></div>
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The operation of the circuit is as follows.</div>
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<li>The register is first cleared, forcing all four outputs to zero.</li>
<li>The input data is then applied sequentially to the D input of the first flip-flop on the left (FF0).</li>
<li>During each clock pulse, one bit is transmitted from left to right.</li>
<li>Assume a data word to be 1001.</li>
<li>The least significant bit of the data has to be shifted through the register from FF0 to FF3.</li>
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In order to get the data out of the register, they must be shifted out serially. This can be done destructively or non-destructively. For destructive readout, the original data is lost and at the end of the read cycle, all flip-flops are reset to zero.<br />
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<img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEipn2bGWThwLEgc5IHMNhem4kOZ5AmX4d7v-kyIzUFOAizDNa6zONU-Qp53MH9QGqQsq4WbqqA_EcAFSi_Mj_i6cOsutUveSZAIIhMwNk_YTztGwitS1ZJOwbrbojf4-5_dUVhAIAGvaSHh/s1600/SISO1.JPG" /></div>
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The data is loaded to the register when the control line is HIGH (i.e. WRITE). The data can be shifted out of the register when the control line is LOW (i.e. READ).</div>
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<img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjvnLnLGNMlI1gqjnZ7lHxXT49VGwQUF9ngNozUBRb0BRtdkntsF6cDIy9G83ZkFg60LCL6-9yLZlon2qVhLDxIrpnRTSsQLCYAM26M1l7V7qKx65iknoFVt7EXoCPV2PQkIPw2ChIfQCWK/s1600/SISO2.JPG" /></div>
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<b><span style="color: #3d85c6;">Serial In - Parallel Out Shift Registers</span></b></div>
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For this kind of register, data bits are entered serially in the same manner as discussed in the last section. The difference is the way in which the data bits are taken out of the register. Once the data are stored, each bit appears on its respective output line, and all bits are available simultaneously. A construction of a four-bit serial in - parallel out register is shown below.<br />
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<img alt="Serial Input Parallel Out Shift Register" border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEioTlOj1zzWG3B2hKtuWVeX6t1Mt2vn5_UvlNN9TN516GhNr6J2Xxt81D1E35KUqpSXiUxX8R8_rB_3xmsuZH-_EFbZ9tlkhZdnAizTqEbJTlLSqnZEvK3DCetduup5savDOsBnOqAYFabk/s1600/SIPO.JPG" title="Serial Input Parallel Out Shift Register" /></div>
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In the table below, we can see how the four-bit binary number 1001 is shifted to the Q outputs of the register.</div>
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<img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjKgjkXTj7X_GRn1S4UZIsiwTRRfU3Vk2YjYtCo7ibeR2b9yBAZKxelQfmKXUlFYwAeNQFnAsZpejJQMJS13CuA1k7Ni54ZPw2q3zdUDi74c1E85Q_d0EeKp0QEjIwrTUzWn2D5HDxsXrps/s1600/SIPO1.JPG" /></div>
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<b><span style="color: #3d85c6;">Parallel In - Serial Out Shift Registers</span></b></div>
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A four-bit parallel in - serial out shift register is shown below. The circuit uses D flip-flops and NAND gates for entering data (i.e. writing) to the register.<br />
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<a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEi9fokGdjj2WbcWbBYlRlOFFvQFsFxbcWdD1FsZt2_6Gq5WEl2GYz52PmTYDHjBcd0lGzsy3k58uVLvn5u2wS7tyRfqKiFqdLiwWWC5qP2euCquBCaVdnE-FxEVVykxpd3epFnUHZ76rhVs/s1600/PISO.JPG" imageanchor="1" style="margin-left: 1em; margin-right: 1em;"><img alt="Parallel Input Serial Out Shift Register" border="0" height="227" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEi9fokGdjj2WbcWbBYlRlOFFvQFsFxbcWdD1FsZt2_6Gq5WEl2GYz52PmTYDHjBcd0lGzsy3k58uVLvn5u2wS7tyRfqKiFqdLiwWWC5qP2euCquBCaVdnE-FxEVVykxpd3epFnUHZ76rhVs/s1600/PISO.JPG" title="Parallel Input Serial Out Shift Register" width="640" /></a></div>
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D0, D1, D2 and D3 are the parallel inputs, where D0 is the most significant bit and D3 is the least significant bit. To write data in, the mode control line is taken to LOW and the data is clocked in. The data can be shifted when the mode control line is HIGH as SHIFT is active high. The register performs right shift operation on the application of a clock pulse, as shown in the table below.</div>
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<img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjhvgpdFRG0eVFRq9Bkhtxt6z1VxkJTP2xwqDFm6e6t13e52VsdsCNLbw6smNMQlmQ16dWRMMUWjQ11UI24dxOUU-hzsrAkVYhkonCyjof22uee_y1OvSnVLRPgRbssA6ciOk_CiQoou-lD/s1600/PISO1.JPG" /></div>
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<b><span style="color: #3d85c6;">Parallel In - Parallel Out Shift Registers</span></b></div>
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For parallel in - parallel out shift registers, all data bits appear on the parallel outputs immediately following the simultaneous entry of the data bits. The following circuit is a four-bit parallel in - parallel out shift register constructed by D flip-flops.<br />
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<img alt="Parallel Input Parallel Out Shift Register" border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEiTGpoJpC7rI6ItXDrpy8Ao9ZyhXmxVtzyDzMfTBTPT2Wlq5S5fMeVkCLPBBSM4MMVMxdpWb79QtMYENgUGje-zVXIS4MO_gqdtPdEv71EqFlZ_qC5fejlv6xRv0HBI6nUpSwSsALhmKT_j/s1600/PIPIO.JPG" title="Parallel Input Parallel Out Shift Register" /></div>
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The D's are the parallel inputs and the Q's are the parallel outputs. Once the register is clocked, all the data at the D inputs appear at the corresponding Q outputs simultaneously.</div>
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<b><span style="color: #3d85c6;">Bidirectional Shift Registers</span></b></div>
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The registers discussed so far involved only right shift operations. Each right shift operation has the effect of successively dividing the binary number by two. If the operation is reversed (left shift), this has the effect of multiplying the number by two. With suitable gating arrangement a serial shift register can perform both operations.</div>
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A bidirectional, or reversible, shift register is one in which the data can be shift either left or right. A four-bit bidirectional shift register using D flip-flops is shown below.<br />
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<a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjZq8DwPS71x3X6JSCjiFhq_Et18xiNPMyv2wkfFICF8m_e4X60SvfrV2HwiNupusEJ-ghyphenhyphenVFEqVkzoX5IsUbPQUztZTtwn4VP5Q8XsKWFmuKwfgmUd4dIe9F_vI0uCs4ACEvuKB6lg4tTv/s1600/Bidirectional+Shift+register.JPG" imageanchor="1" style="margin-left: 1em; margin-right: 1em;"><img alt="Bidirectional Shift Registers" border="0" height="241" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjZq8DwPS71x3X6JSCjiFhq_Et18xiNPMyv2wkfFICF8m_e4X60SvfrV2HwiNupusEJ-ghyphenhyphenVFEqVkzoX5IsUbPQUztZTtwn4VP5Q8XsKWFmuKwfgmUd4dIe9F_vI0uCs4ACEvuKB6lg4tTv/s1600/Bidirectional+Shift+register.JPG" title="Bidirectional Shift Registers" width="640" /></a></div>
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Here a set of NAND gates are configured as OR gates to select data inputs from the right or left adjacent bistables, as selected by the LEFT/RIGHT control line.</div>
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Shift Registers

The binary data in a register can be moved within the register from one flip-flop to the other or outside it with application of clock pul...

Demultiplexer

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A decoder/demultiplexer is a combinational circuit that asserts one of several outputs in response to a unique input code. It is a unit with n-inputs and m-outputs, where m < <span style="background-color: #ffffcc; color: #333333; font-family: 'Open Sans', 'Helvetica Neue', Arial, Helvetica, sans-serif; line-height: 25px;">2<sup style="margin: 0px; padding: 0px;"><span style="font-family: 'Times New Roman', serif; line-height: 15.3333320617676px; margin: 0px; padding: 0px;">n</span></sup></span>. An output switches from Not Asserted state to an Asserted state, when the input code is switched to a specific one. When m = <span style="background-color: #ffffcc; color: #333333; font-family: 'Open Sans', 'Helvetica Neue', Arial, Helvetica, sans-serif; line-height: 25px;">2</span><sup style="color: #333333; font-family: 'Open Sans', 'Helvetica Neue', Arial, Helvetica, sans-serif; line-height: 25px; margin: 0px; padding: 0px;"><span style="font-family: 'Times New Roman', serif; line-height: 15.3333320617676px; margin: 0px; padding: 0px;">n</span></sup>, each one of the outputs can be associated with a Minterm of n-variables. Hence, such a decoder is known as Minterm Recogniser. Schematic of a 3-input demultiplexer is shown in figure below.<br />
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<img alt="3-input demultiplexer" border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEggJw-d6TxBVmmyRUbHc2qExPJeAW23TW-ClVqTlfXXYOFEUNtsLK7SzdEu59kWwgsyeFTAzT9ECSw9ApdyZYuARQ416ZgqgellJynu_VS_X3gsBaB0U5__zryXNu1ndE-9aoZJopq60BW8/s1600/Demux.JPG" title="3-input demultiplexer" /></div>
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<b>Schematic of a 3-input demultiplexer</b></div>
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In the demultiplexer illustrated, each one of the outputs have an AND (G) dependence on one of the input codes, while, Enable inputs can be used to disable/enable the entire functional unit.</div>
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<b>Decoding and Demultiplexing Functions</b></div>
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One of the traditional uses of a demultiplexer is to use it in combination with a multiplexer to transmit a number of signals over a single line. An 8-channel multiplexer-demultiplexer combination is shown in the figure below.</div>
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<img alt="An 8-channel multiplexer-demultiplexer combination" border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEih3iahX9Pj2i36qIyBJE_RXXhY3T6taXXQuucrCbFbKoisQj8lUMqdlVrx7XgvuvWfl2aNkS3VNTvR2n9IGyhKUke0tYEpuTjhYMkfJMSj9GWU992IxqkshoEeCiFuh0l0F0wLng2irGme/s1600/Demux1.JPG" title="An 8-channel multiplexer-demultiplexer combination" /></div>
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<b>An 8-channel multiplexer-demultiplexer combination</b></div>
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Notice that one of the Enable inputs of the demultiplexers is used as its data input. Though this illustration indicates that the address lines are tied together, in an actual signal transmission unit that uses such a MUX-DEMUX combination a different method will have to be used to change the addresses of both the units simultaneously.</div>
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Demultiplexer

A decoder/demultiplexer is a combinational circuit that asserts one of several outputs in response to a unique input code. It is a unit wi...

Multiplexer

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A multiplexer is a combinational circuit that gates one out of its several inputs to a single output. As it selects one out of many inputs, it is also called a “data selector”. The input selected for connection to the output is controlled by a set of SELECT inputs. A typical 4-input multiplexer is illustrated in the figure below.<br />
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<img alt="Schematic of a 4-input multiplexer" border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjzL3QlLSJNNOcSwUkKJK-M3rG9i7J6QFDEuDx41tFvMoa31ti01kYbbgkurEjJJD3a8ZKevfm_ddxJT04-25nAxKLfjRuX1ks6tZkwOj_M0dzhPjMfQmdFP1wuJgHRZiS1n_0ETHLNP1v4/s1600/multiplexer.JPG" title="Schematic of a 4-input multiplexer" /></div>
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<b>Figure: Schematic of a 4-input multiplexer</b></div>
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S0 and S1 are select inputs. Together S0 and S1 determine the input, among the Data Inputs, DI0, DI1, DI2, and DI3, that gets connected to the output Y.</div>
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The output of the multiplexer is given by:</div>
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<img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEiWSX1Ah-ENRBVRc4nk-VRRVESwQPfSRYX0OhSyp38G5K3EOCuqGT-P7Xa1TDC0d7gI0ZFDT7a86I57Ke4SPbFwkHlGbkS_0JAL4rd8JuKeX6p5mR-AGDC5scjgtLouOQwyU9TuSeEujn_v/s1600/multi.JPG" /></div>
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Notice that the relationship between the SELECT inputs and the DATA inputs is G dependency.</div>
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The main parameters of concern to us are:</div>
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<li>Number of inputs</li>
<li>Nature of outputs</li>
<li>Propagation delay</li>
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The choice on the number of inputs enables us to select the appropriate multiplexer, to minimize the number of ICs needed to implement a given logic function.</div>
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For example, if data is to be selected from two 16-bit sources, it is more convenient to use 2-input multiplexers, than 4-input or 8-input multiplexers.</div>
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Some additional features:</div>
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<li>Higher drive capability of a multiplexer enables the designer to save on buffers and the consequent delay in certain situations.</li>
<li>Availability of complementary outputs often results in the saving of additional inverters.</li>
<li>Availability of tri-state outputs make it easy to tie the outputs of a number of multiplexers without using additional gates.</li>
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There are two propagation delays that are of interest to designers:</div>
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<li>Delay from the data inputs to the output</li>
<li>Delay from the select input to the output</li>
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These timing relationships are shown in figure below.<br />
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<b>Timing relationship between signals of a multiplexer</b></div>
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<b>Data Selection</b></div>
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The multiplexer was mainly designed for selecting data from several sources. For example, if we are required to select an 8-bit data from one of four possible sources, then, it can be realized through four dual 4-input multiplexers, like 74LS153. The circuit that realizes such a data selection is shown in figure below.</div>
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<img alt="Circuit for selecting 8-bit data from four sources" border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEimvD2HqC-QrGWX6_69utcGzb6lo-euS0MBNEXJs06AL0jI3cRU8SFGA1D1u3bgnYy360KmOqyS2gTxUW6yhPDJ0MmcXt0Uvj5zccy3pB6IBDp-jXZK7Km4Ow15tGs-86eUAUPg4k8jG_E2/s1600/Data1.JPG" title="Circuit for selecting 8-bit data from four sources" /></div>
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<b>Circuit for selecting 8-bit data from four sources</b></div>
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Another conventional use of the multiplexers is one of time-division gating of several data lines on to a transmission channel using SELECT lines. This is done by using a `Multiplexer' as the sending unit, and a `Demultiplexer' as a receiving unit. The sending end of such a transmission system which multiplexes 32 data lines is shown in Figure below.</div>
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<img alt="1-of-32 data selector" border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEg5xSfpl6wPmi_xC212DJJ8UvLJZrqsSFlm-B0-tYu32xJY27uysWEJr8NTILlTfldlewynF1CA9j1JaALX0Zp8lY1djTgorwoR-ZZZkdYy0-n04cZdd96sM24GqYCIs9JEnXaJta-Htz2r/s1600/Data.JPG" title="1-of-32 data selector" /></div>
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<b>1-of-32 data selector</b></div>
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Multiplexer

A multiplexer is a combinational circuit that gates one out of its several inputs to a single output. As it selects one out of many inputs...

Sequential Circuits

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In the sequential circuit, the timing parameter comes into picture.</div>
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The output of a sequential circuit depends on the present time inputs, the previous output and the sequence in which the inputs are applied.</div>
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In order to provide the previous input or output a memory element is required to be used. Thus a sequential circuit needs a  memory element.<br />
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<img alt="Block diagram of a sequential circuit" border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEh4WMN1RlxFNC_38WMguCkWNAfio4WUBVnIZnUvgI4MuRtweWdltwYXq-SH8fU6Yje2S5V84dbLZKfP7pZ9pHpZm0E2jsb4eGbhYsDY5wg1fzrAfNm4iWeZJPSPpp7fLbO2BJSa1NVBVxHS/s1600/sequential+circuit.png" title="Block diagram of a sequential circuit" /></div>
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<b>Figure 1</b></div>
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Figure 1 shows the block diagram of a sequential circuit which includes the memory element in the feedback path.</div>
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<b>Present state of sequential circuit:</b> The data stored by the memory element at any given instant of time is called as the present state of the sequential circuit.</div>
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<b>Next state:</b> The combinational circuit operates on the external inputs and the present state to produce new outputs. Some of these new outputs are stored in the memory element  and called as the next state of the sequential circuit.</div>
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The most important part of the sequential circuit seems to be the memory element. The memory element is known as flip flop (FF). It is the basic memory element.</div>
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<b><span style="color: #3d85c6;">Clock Signal:</span></b> The clock signal is a timing signal. Every sequential signal will have this timing signal applied.</div>
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Clock is a rectangular signal with a duty cycle equal to 50%.</div>
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The clock signal repeats itself after every T seconds. Hence the clock frequency is f = 1/T.</div>
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Sequential Circuits

In the sequential circuit, the timing parameter comes into picture. The output of a sequential circuit depends on the present time inp...

NOR and NAND Architecture

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NOR architecture is one of two technologies (the other being NAND) used in memory cards. NOR flash is the preferred technology for flash devices used to store and run code, usually in small capacities. NOR flash devices offer storage space up to 32-MB and while it has fast read capabilities it has slow write and slow erase functions compared to the NAND architecture. NOR technology is more commonly found as embedded designs and in lower-end set-top boxes and mobile handsets, and BIOS chips.</div>
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NOR flash architecture was introduced by Intel in 1988.</div>
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NAND Flash architecture is one of two flash technologies (the other being NOR) used in memory cards such as the CompactFlash cards. It is also used in USB Flash drives, MP3 players, and provides the image storage for digital cameras. NAND is best suited to flash devices requiring high capacity data storage. NAND flash devices offer storage space up to 512-MB and offers faster erase, write, and read capabilities over NOR architecture.</div>
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NAND flash architecture was introduced by Toshiba in 1989.</div>
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<b>NOR ARCHITECTURE</b></div>
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Here every cell is connected in NOR fashioned manner as shown in Fig. 1.1(a). Note that the transistors used are FG type and two gates can be seen in their symbols. Every source terminal of the transistor is connected to ground in NOR architecture. Metal lines are required between each individual cell to run the ground in NOR architectures and therefore they occupy more area. NOR-based flash has long erase and write times, but has a full address/data (memory) interface that allows random access to any location. This makes it suitable for storage of program code that needs to be infrequently updated, such as computers' BIOS.</div>
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<b>NAND ARCHITECTURE</b></div>
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In the NAND structure, a series of floating gate transistors are connected between the bit line and ground line. This organization allows the elimination of all contacts to ground line and thus reducing the area by 40% compared to NOR architecture. It has faster erase and write times, higher density, and lower cost per bit than NOR flash. This can be obtained by arranging 8 to 16 floating gate transistors connected in series as shown in the Fig. 1.1(b). However, its I/O interface allows only sequential to data. This makes it suitable for mass-storage devices such as PC cards and various memory stick cards.</div>
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NOR and NAND Architecture

NOR architecture is one of two technologies (the other being NAND) used in memory cards. NOR flash is the preferred technology for flash d...

Non-Volatile Memories

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Based on the programmability of the devices non-volatile memories are categorized as follows. Writing data into ROMs is possible only at the time of manufacturing the devices and used only for reading the data stored. Even though these devices are less in cost the constraint that they are to be programmed at the time of manufacturing is an inconvenience. PROM devices are one time programmable ROM. At the time of device manufacturing every cell is stored with "1" and can be programmed by customer once. But, single write phase makes them unattractive. For instance, a single error in the programming process or application makes the device unusable.</div>
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EPROM is Erasable PROM. Multiple times programming feature is added in EPROM. In this case, first whole memory is to be erased by shining ultraviolet light. The erase process is slow and can take from seconds to several minutes, depending on the intensity of the UV source. Programming takes several (5-10) <span style="font-family: 'Times New Roman', serif; font-size: 12pt; line-height: 115%; text-align: left;">μs</span>/word. EPROM cell is extremely simple and dense, making it possible to fabricate large memories at a low cost. EPROMs were therefore attractive in applications that not require frequent programming. Electrically-Erasable PROM (EEPROM) can be erased without removing from board, unlike in UV erasable where memory must be removed from the board. The voltage approximately applied for programming is 18V. In addition, it is a reverse process; means by applying high negative voltage at gate can erase the cell. Another advantage over EPROM is that EEPROM can be programmed for <span style="font-family: 'Times New Roman', serif; font-size: 12pt; line-height: 115%;">10<sup>5</sup></span> cycles.</div>
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Flash Electrically Erasable PROM Technically the Flash EEPROM is a combination of the EPROM and EEPROM approaches. The main difference is that erasure can be performed for the complete chip, or for a sub-section of the memory. The control circuits on the memory chip can be regularly checked for the value of the threshold during erasure, and the erasure time can be adjusted dynamically. Flash technology has three basic weaknesses. First, its bulk erase nature prevents the use of normal byte-oriented update. Second, Based on the architecture used write and erase operations take different time and consume more power than read. Finally, each flash-memory block has a limitation on the erase cycle count.</div>
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Although transistors are used for realization of Read Only Memory, the functioning of Rom can be easily understood by diode matrix network depicted in Fig. 1. In this network, whichever switch is closed, those diodes will conduct and the output will be high (logic 1), sections where there is no diode connected there will be no current flowing and the output will be low (logic 0). For instance, when switch S5 is closed, the diodes D6 and D7 are on and therefore both output 1 and output 3 are at logic 1 and both output 2 and output 4 are at logic 0. Hence the corresponding binary number is 0101 and its decimal value is 5.</div>
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The disadvantage of a diode cell is that it does not isolate the bit line from the word line. For better isolation the diode can be replaced by gate-source connection of a NMOS transistor. Moreover, in order to achieve the programmability i.e. for multiple read write capability a modified transistor known as Floating Gate (FG) Transistor is employed. The structure is similar to a traditional MOS device, except that an extra gate is inserted between gate and channel. The threshold voltage of the FG is programmable and corresponding to its different values the level 0 and level 1 can be identified.</div>
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<img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjXOWJefr6xafvroXUCNKcfm1FxqzLZkl3EsnRw27fd8bi7saSG-sNdPZdl9-E18Mh8Tdr_wPlvjrBP-pt9_P9hSYyEBetRcPDoqV10A7wwVdMMi2fxkfeztcT87qAVPP0sbf8z6-sAWY4_/s1600/A+Diode+ROM+Matrix.png" /></div>
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<b><i>Fig. 1 : A Diode ROM Matrix</i></b></div>
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Flash memory cells can be arranged in two popular architectures; the NOR and the NAND architectures as explained in the following sections.</div>
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Non-Volatile Memories

Based on the programmability of the devices non-volatile memories are categorized as follows. Writing data into ROMs is possible only at t...

Volatile Memories

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<span style="font-family: inherit;">Static Random Access Memory (SRAM) and Dynamic Random Access Memory (DRAM) are volatile memories. SRAM is used as a cache memory in computers since it offers the fastest write/read (~8ns) speed among all memories. Hardware design of a single SRAM cell consists of 6 transistors. A DRAM cell consists of one transistor and one capacitor and it is based on the charge stored in a capacitor. It is superior to SRAM because of its low cost per bit storage; nevertheless it is slower (`50ns). In DRAM, the stored charge in the capacitor can be maintained only for few milli-seconds and therefore, an extra hardware circuit is needed to periodically refresh the data periodically.</span></div>
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<b>Static Random Access Memory (SRAM)</b></div>
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A single SRAM memory cell is shown in Figure below.  Two NMOS and two PMOS transistors (M1 to M4) forms the simple latch to store the data and two pass NMOS transistors (M5 and M6) are controlled by Word Line to pass Bit Line and <span style="font-family: "Times New Roman","serif"; font-size: 12.0pt; line-height: 115%; mso-ansi-language: EN-US; mso-bidi-language: AR-SA; mso-fareast-font-family: Calibri; mso-fareast-language: EN-US; mso-fareast-theme-font: minor-latin;">~</span>Bit Line  into the cell.</div>
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A <b>Write</b> operation is performed by first charging the Bit Line and <span style="font-family: "Times New Roman","serif"; font-size: 12.0pt; line-height: 115%; mso-ansi-language: EN-US; mso-bidi-language: AR-SA; mso-fareast-font-family: Calibri; mso-fareast-language: EN-US; mso-fareast-theme-font: minor-latin;">~</span>Bit Line with values that are desired to be stored in the memory cell. Setting the Word Line high performs the actual write operation, and the new data is latched into the circuit.</div>
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A <b>Read</b> operation is initiated by pre-charging both Bit Line and <span style="font-family: "Times New Roman","serif"; font-size: 12.0pt; line-height: 115%; mso-ansi-language: EN-US; mso-bidi-language: AR-SA; mso-fareast-font-family: Calibri; mso-fareast-language: EN-US; mso-fareast-theme-font: minor-latin;">~</span>Bit Line to logic 1. Word Line is set high to close NMOS pass transistors to put the contents stored in the cell on the Bit Line and <span style="font-family: "Times New Roman","serif"; font-size: 12.0pt; line-height: 115%; mso-ansi-language: EN-US; mso-bidi-language: AR-SA; mso-fareast-font-family: Calibri; mso-fareast-language: EN-US; mso-fareast-theme-font: minor-latin;">~</span>Bit Line.</div>
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Transistors M1 to M4 constitute the latch and are constantly toggling back and forth. During these switching the power consumption in CMOS circuits takes place and therefore, the sizes of these transistors are kept as small as possible. NMOS transistors are basically switches opening and closing access to the SRAM cell. To minimize the propagation delay caused by these transistors their sizes are kept relatively larger.</div>
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<img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEielY01bTwoheoq3CntM5A-qqjxpVCRplFjapVy3G4nzSoywjKOosqEr5-XJPnBtPKFgOgrl4Y9XNSSE2Z6KbCGSpeN4XKEA01i6d0JRL2yX6yPJ8dSB_gPkzi7WV4u0kwrkCnNfWY0gx-o/s1600/SRAM.png" /></div>
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<b>Dynamic Random Access Memory (DRAM)</b></div>
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DRAM stores each bit in a storage cell consisting of a capacitor and a transistor. Capacitors tend to lose their charge rather quickly; thus, the need for recharging. The presence or absence of charge in the capacitor determines whether the cell contains a '1' or a '0'. The <b>Read</b> operation begins by precharging the bit line to an intermediate value, <span style="font-family: 'Times New Roman', serif; font-size: 12pt; line-height: 115%;">V</span><sub style="font-family: 'Times New Roman', serif; line-height: 115%;">DD</sub><span style="font-family: 'Times New Roman', serif; font-size: 12pt; line-height: 115%;"> / 2</span>. The word line is raised to a high potential and the charge stored on capacitor is shared with <span style="font-family: 'Times New Roman', serif; font-size: 12pt; line-height: 115%;">V</span><sub style="font-family: 'Times New Roman', serif; line-height: 115%;">DD</sub><span style="font-family: 'Times New Roman', serif; font-size: 12pt; line-height: 115%;"> / 2</span> that on the bit line. The change in the bit line voltage is given by the change on the bit line capacitor when the charge stored on capacitor C is shared with the bit line.</div>
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During the ' <b>Write 1</b> ' operation, the word line is driven high, the bit line is tied to VDD corresponding to a 1, and voltage across C rises toward <span style="font-family: 'Times New Roman', serif; font-size: 12pt; line-height: 18.3999996185303px;">V</span><sub style="font-family: 'Times New Roman', serif; line-height: 15.3333320617676px;">DD</sub> - <span style="font-family: 'Times New Roman', serif; font-size: 12pt; line-height: 18.3999996185303px;">V</span><sub style="font-family: 'Times New Roman', serif; line-height: 15.3333320617676px;">tn</sub> . To ' <b>Write 0 </b>' in the cell, the bit line is grounded during the write operation and 0V is stored on capacitor C.</div>
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Volatile Memories

Static Random Access Memory (SRAM) and Dynamic Random Access Memory (DRAM) are volatile memories. SRAM is used as a cache memory in comput...

Semiconductor Memories

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Semiconductor memories are classified in different ways. A distinction is made between read-only (ROM) and read-write (RWM) memories. The contents RWMs can be changed in a short time for a virtually unlimited number of times and contents of ROMs are mostly useful for frequent reading and occasional writing. Since RWM memories use active circuitry (transistors) to store the information, they belong to the class of called volatile memories. This is because the data would be lost when the supply voltage is turned off. Read-only memories, on the other hand, encode information by the presence or absence of devices. Their data cannot be modified and they belong to the class of nonvolatile memories. That means the stored data is lost by the disconnection of supply voltage.</div>
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<b><i>Table 1: Classification of  Semiconductor Memories</i></b></div>
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Based on the access pattern, RWMs are classified as random access class and serial memories. FIFO (first-in-first-out) is an example for serial memories. Most memories belong to the random access class, which means memory locations can be read or written in random order. One would expect memories of this class to be called RAM (random access memory); nevertheless for historic reasons, RAM has been reserved for random access RWM memories. That means though most ROM units also provide random access, but the acronym RAM should not be used for them.</div>
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Types of Semiconductor Memories:</div>
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<li><b>Volatile Memories:</b> Static Random Access Memory (SRAM) and Dynamic Random Access Memory (DRAM) are volatile memories. SRAM is used as a cache memory in computers since it offers the fastest write/read (~8ns) speed among all memories. A DRAM cell consists of one transistor and one capacitor and it is based on the charge stored in a capacitor.</li>
<li><b>Non-Volatile Memories:</b> Non-volatile memory is computer memory that can get back stored information even when not powered. Examples of non-volatile memory include read-only memory, flash memory, most types of magnetic computer storage devices (e.g. hard disks, floppy disks, and magnetic tape), optical discs, and early computer storage methods such as paper tape and punched cards.</li>
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Semiconductor Memories

Semiconductor memories are classified in different ways. A distinction is made between read-only (ROM) and read-write (RWM) memories. The ...

Transistor-Transistor Logic (TTL)

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<span style="font-family: inherit;">TTL is the short form of Transistor Transistor Logic. As the name suggests they refers to the digital integrated circuits that employ logic gates consisting primarily of bipolar transistors. The most basic TTL circuit is an inverter. It is a single transistor with its emitter grounded and its collector tied to V<sub>CC </sub>with a pull-up resistor, and the output is taken from its collector. When the input is high (logic 1), the transistor is driven to saturation and the output voltage i.e. the drop across the collector and emitter is negligible and therefore output voltage is low (logic 0).</span><br />
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<span style="font-family: inherit;">A two input NAND gate can be realized as shown in Fig.1a. When, at least any one of the input is at logic 0, the multiple emitter base junctions of transistor T<sub>A</sub> are forward biased whereas the base collector is reverse biased. The transistor T<sub>A</sub> would be ON forcing a current away from the base of T<sub>B </sub>and thereby T<sub>B</sub> is OFF. Almost all V CC would be dropping across an OFF transistor and the output voltage would be high (logic l). For a case when both Input 1 and Input 2 are at V<sub>CC</sub> , both the base emitter junctions are reverse biased and the base collector junction of the transistor T<sub>A</sub> is forward biased therefore the transistor T<sub>B</sub> is on making the output at logic 0, or near ground.</span><br />
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<span style="font-family: inherit;">However, most TTL circuits use a totem pole output circuit instead of the pull-up resistor as shown in Fig.1b. It has a V<sub>CC</sub> -side transistor (T<sub>C</sub>) sitting on top of the GND-side output transistor (T<sub>D</sub>). The emitter of the T<sub>C</sub> is connected to the collector of T<sub>D</sub> by a diode. The output is taken from the collector of transistor T<sub>D</sub>. T<sub>A</sub> is a multiple emitter transistor having only one collector and base but with multiple emitters. The multiple base emitter junction behaves just like an independent diodes. Applying a logic '1' input voltage to both emitter inputs of T<sub>A</sub> reverse-biases both base-emitter junctions, causing current to flow through R <sub>A</sub> into the base of T<sub>B</sub>, which is driven into saturation. When T<sub>B</sub> starts conducting, the stored base charge of T<sub>C</sub> dissipates through the T<sub>B</sub> collector, driving T<sub>C</sub> into cut-off. On the other hand, current flows into the base of T<sub>D</sub> , causing it to saturate and its collector emitter voltage is 0.2 V and the output is equal to 0.2 V, i.e. at logic 0. In addition, since T<sub>C</sub> is in cut-off, no current will flow from V<sub>CC</sub> to the output, keeping it at logic '0'. Since T<sub>D</sub> is in saturation, its input voltage is ~0.8 V. Therefore the output voltage at the collector of transistor T <sub>B</sub> is 0.8 V + V<sub>CESat</sub> (saturation voltage between conductor and emitter of a transistor is equal to ~0.2 V) = 1 V. T B always provides complementary inputs to the bases of T<sub>C</sub> and T<sub>D</sub>, such that T<sub>C</sub> and T<sub>D</sub> always operate in opposite regions, except during momentary transition between regions. The output impedance is low independent of of the logic state because one transistor (either T<sub>C</sub> or T<sub>D </sub>) is ON.</span><br />
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<span style="font-family: inherit;">When at least one of inputs are at 0 V, the multiple emitter base junctions of transistor T<sub>A </sub>are forward biased whereas the base collector is reverse biased and transistor T<sub>B</sub> remains off and therefore the output voltage is equal to V<sub>CC</sub> . Since the base voltage for transistor T<sub>C</sub> is V<sub>CC</sub> , this transistor is on and the output is also V<sub>CC</sub> . And the input to transistor T<sub>D</sub> is 0 V, hence it remains off.</span><br />
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<span style="font-family: inherit;">TTL overcomes the main problem associated with DTL (Diode Transistor Logic), i.e., lack of speed. The input to a TTL circuit is always through the emitter(s) of the input transistor, which exhibits a low input resistance. The base of the input transistor, on the other hand, is connected to the V<sub>CC</sub> , which causes the input transistor to pass a current of about 1.6 mA when the input voltage to the emitter(s) is logic '0'. Letting a TTL input 'float' (left unconnected) will usually make it go to logic '1'. However, such a state is vulnerable to stray signals, which is why it is good practice to connect TTL inputs to V<sub>CC </sub>using 1 k-ohm pull-up resistors.</span></div>
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Transistor-Transistor Logic (TTL)

TTL is the short form of Transistor Transistor Logic. As the name suggests they refers to the digital integrated circuits that employ logi...

Canonical and Standard forms

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A binary variable may be either in its true form <i>A</i> or its complement <span style="font-family: Calibri, sans-serif; font-size: 12pt; line-height: 115%; text-align: left;"><i>Ᾱ</i></span>. For n variables, the maximum number of input variable combinations is given by N = 2<sup><span style="font-family: Times, Times New Roman, serif; font-size: 12pt; line-height: 115%;">n</span></sup>. Then considering the AND gate, each of the N logic expressions formed is called a standard product or minterm. As indicated in Table 1, binary digits '1' and '0' are taken to represent a given variable for example <i>A</i> or its complement <span style="font-family: Calibri, sans-serif; font-size: 12pt; line-height: 115%; text-align: left;"><i>Ᾱ</i></span> respectively. Also from Table 1 note that each minterm is assigned a symbol (P j) each where j is the decimal equivalent to the binary number of the minterm designated.</div>
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Similarly, if we consider an OR gate, each of the N logic expressions formed is called a standard sum or maxterm. In this case binary digits '1' and '0' are taken to represent a given complemented variable <span style="font-family: Calibri, sans-serif; font-size: 12pt; line-height: 115%; text-align: left;"><i>Ᾱ</i></span> and its true form <i>A</i> respectively. As shown in Table 1, a symbol (S j) is assigned to each maxterm where j is the decimal equivalent to the binary number of the maxterm designated. Also observe that each maxterm is the complement of its corresponding minterm, and vice versa.</div>
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<b><i>Table 1</i></b></div>
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The minterms and maxterms may be used to define the two standard forms for logic expressions, namely the sum of products (SOP), or sum of minterms, and the product of sums (POS), or product of maxterms. These standard forms of expression aid the logic circuit designer by simplifying the derivation of the function to be implemented. Boolean functions expressed as a sum of products or a product of sums are said to be in canonical form. Note the POS is not the complement of the SOP expression.<br />
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<b>SUM OF PRODUCTS (OR of AND terms)</b><br />
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The SOP expression is the equation of the logic function as read off the truth table to specify the input combinations when the output is a logical 1. To illustrate, let us consider Table 2.<br />
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<b><i>Table 2</i></b></div>
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Observe that the output is high for the rows labelled 3, 5 and 6. The SOP expression for this circuit is thus given any of the following:<br />
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 F = P <sub><span style="font-family: "Times New Roman","serif"; font-size: 12.0pt; line-height: 115%; mso-ansi-language: EN-US; mso-bidi-language: AR-SA; mso-fareast-font-family: Calibri; mso-fareast-language: EN-US; mso-fareast-theme-font: minor-latin;">3</span></sub> + P <sub><span style="font-family: "Times New Roman","serif"; font-size: 12.0pt; line-height: 115%; mso-ansi-language: EN-US; mso-bidi-language: AR-SA; mso-fareast-font-family: Calibri; mso-fareast-language: EN-US; mso-fareast-theme-font: minor-latin;">5</span></sub> + P <span style="font-family: 'Times New Roman', serif; font-size: 12pt; line-height: 115%; text-align: justify; vertical-align: sub;">6</span></div>
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Each product (AND) term is a Minterm. ANDed product of literals in which each variable appears exactly once, in true or complemented form (but not both). Each minterm has exactly one '1' in the truth table. When minterms are ORed together each minterm contributes a '1' to the final function. Note that all product terms are not minterms.</div>
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<b>PRODUCT OF SUMS ( AND of OR terms)</b></div>
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The POS expression is the equation of the logic function as read off the truth table to specify the input combinations when the output is a logical 0. To illustrate, let us again consider Table 2. Observe that the output is low for the rows labeled 0, 1, 2, 4 and 7. The POS expression for this circuit is thus given by any of the following:</div>
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 F = S<sub><span style="font-family: "Times New Roman","serif"; font-size: 12.0pt; line-height: 115%; mso-ansi-language: EN-US; mso-bidi-language: AR-SA; mso-fareast-font-family: Calibri; mso-fareast-language: EN-US; mso-fareast-theme-font: minor-latin;">0</span></sub> S<sub><span style="font-family: "Times New Roman","serif"; font-size: 12.0pt; line-height: 115%; mso-ansi-language: EN-US; mso-bidi-language: AR-SA; mso-fareast-font-family: Calibri; mso-fareast-language: EN-US; mso-fareast-theme-font: minor-latin;">1</span></sub> S<sub><span style="font-family: "Times New Roman","serif"; font-size: 12.0pt; line-height: 115%; mso-ansi-language: EN-US; mso-bidi-language: AR-SA; mso-fareast-font-family: Calibri; mso-fareast-language: EN-US; mso-fareast-theme-font: minor-latin;">2</span></sub> S<sub><span style="font-family: "Times New Roman","serif"; font-size: 12.0pt; line-height: 115%; mso-ansi-language: EN-US; mso-bidi-language: AR-SA; mso-fareast-font-family: Calibri; mso-fareast-language: EN-US; mso-fareast-theme-font: minor-latin;">4</span></sub> S<span style="font-family: 'Times New Roman', serif; font-size: 12pt; line-height: 115%; text-align: justify; vertical-align: sub;">7</span></div>
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Each OR (sum) term is a Maxterm. ORed product of literals in which each variable appears exactly once, in true or complemented form (but not both). Each maxterm has exactly one '0' in the truth table. When maxterms are ANDed together each maxterm contributes a '0' to the final function. Please note that not all sum terms are maxterms.</div>
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Canonical and Standard forms

A binary variable may be either in its true form A or its complement Ᾱ . For n variables, the maximum number of input variable combinati...

Karnaugh Map (or K-map) Minimization

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The Karnaugh map provides a systematic method for simplifying a Boolean expression or a truth table function. The K map can produce the simplest SOP or POS expression possible. K-map procedure is actually an application of adjacency and guarantees a minimal expression. It is easy to use, visual, fast and familiarity with Boolean laws is not required.</div>
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The K map is a table consisting of N =2<sup><span style="font-family: "Times New Roman","serif"; font-size: 12.0pt; line-height: 115%; mso-ansi-language: EN-US; mso-bidi-language: AR-SA; mso-fareast-font-family: Calibri; mso-fareast-language: EN-US; mso-fareast-theme-font: minor-latin;">n</span></sup> cells, where n is the number of input variables. Assuming the input variable are A and B then the K map illustrating the four possible variable combinations is shown.<br />
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<b><i>Fig 1. Two variable K map</i></b></div>
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Similarly three variable and four variable K-maps can be constructed as shown below<br />
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<b><i>Fig 2. Three variable K map</i></b></div>
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<b><i>Fig 3. Four variable K map</i></b></div>
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For a SOP expression each cell represents one particular combination of the variables in product form. The table format is such that there is a single variable change between any adjacent cells. This is the characteristic the will determine adjacency. This method is typically applicable to limited number of variables (4 ~ 8) and for n > 5 the K map technique becomes impractical unless implemented on computer. Manual errors are possible in translation from Truth Table to K-map, or when grouping of cells not done correctly.<br />
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Basic K-map is a 2-D rectangular array of cells, each K-map represents one bit column of output and each cell contains one bit of output function. The arrangement of cells in array facilitates recognition of adjacent terms and adjacent terms differ in one variable value; equivalent to difference of one bit of input row values, e.g. m6 (110) and m7 (111). The standard Truth Table ordering does not show adjacency. One uses gray code for row order however, it is still hard to see all possible adjacencies. For any cell in 2-D array, there are four direct neighbors (top, bottom, left, right). The 2-D array can therefore show adjacencies of up to four variables. One should not forget that cells are adjacent top to bottom and side to side. The number of TT rows must match number of K-map cells. Watch out for ordering of 10 and 11 rows and columns.<br />
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To simplify a SOP for of a Boolean expression using a K map, first identify all the input combinations that produce an output of logic level 1 and place them in their appropriate K map cell. Consequently, all other cells must contain zero (0). Second, group the adjacent cells that contain 1 in a manner that maximizes the size of the groups but also minimizes the total number of groups. All 1's in the output must be included in a group even if the group is only one cell. Third, as each SOP term represents an AND expression, each ( AND ) grouping is written with only the input variables that are common to the group. Finally, the simplified expression is formed by ORing each of the ( AND ) groups.<br />
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When the input combinations are irrelevant or cannot occur, the output states are in the Truth table and the K map are filled with an X and are referred to as don't care states . The don't cares can work to our advantage during minimization; we can assign either 0 or 1 as needed. When simplifying K maps with don't care states, the contents of the undefined cells (1 or 0) are chosen according to preference. The aim is to enlarge group sizes thereby eliminating as many input variables from the simplified expression as possible. Only those X's that assist in simplifying the function should be included in the groupings. No additional X's should be added that would result in additional terms in the expression. To illustrate let us consider the function specified by Table 1 and its corresponding K map shown in Fig. 8. Note that the two groupings determine that the simplified expression is expressed as<br />
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<b><i>Table 1. Truth Table of the above Function</i></b></div>
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<b><i>Fig 4</i></b></div>
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If two cells have the same value and are next to each other, the terms are adjacent. This adjacency is shown by enclosing them. Groups can have common cells. Group size is a power of 2 and groups are rectangular. You can group 0s or 1s. If '1's are grouped, the expression will be a product term and '0's are grouped the expression will be a sum term. It is important to note when a variable values change as you go cell to cell. This determines how the term expression is formed by the following table. The bottom most row right side cell is having a value "1". It can be represented by the expression:<br />
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Similarly, expressions for individual as well as grouped "1"s are shown in the figure.<br />
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How the minimum expression of a function is determined using a Karnaugh Map? The concept of prime implicants can be used to determine the minimum solution. Single cells or groups that could be part of a larger group are known as implicants and a group that is as large as possible is a prime implicant. Single cells can be prime implicants is they cannot be grouped with any other cell. In the following Karnaugh map, the implicants and prime implicants are marked separately. The term<img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhsT1b7EKunpkAD3QqJsaRUOyZeuebiOEhVqwNRoB95AiObLvkZgpQ91wFciuIBl2YOtKXl4oxhkzgpSwGbbk8qIIpcxCbYtYfUwoIMiTUpquNom71x7Ck59VIr7lVr3KSmQ73kd_Joqqvx/s1600/equn100.png" style="text-align: center;" /> is not a prime implicant because it can be combined with <img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEi3eKsGJcaK8dH2MmWJWtZyQqhOjIOLVYoswdnmfTlzNneuo_jUTpI4UrRXs9JR6KlJN_3ZEMuDwjALtnFQzq1502N7mySUkG3DWgArkJtJ9ysu19zPl50VmT-reWO7Ep3fX_3kHr6MKiTn/s1600/equn130.png" style="text-align: center;" /> or <img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhGTLM2nyI0dfm9kU6RoLWkibnxn2slBqyKAMELZ29p0QSJ4t-yBtju6JZwKAw6kpSc5HjMibI0jD_0Xf9FnZ3h4HGvDcnyIDcDHamUENHHFsOPRtLT_AnsR1m8bXMhowbjabGOiQf6PR5D/s1600/equn140.png" />.<br />
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The minimum SOP expression for a function consists of some (but not necessarily all) of the prime implicants of a function. In other words, a SOP expression containing a term, which is not a prime implicant, cannot be the minimum. This is true because if a nonprime term were present, the expression could be simplified by combining the nonprime term with additional minterms. Any set of implicants that encloses (covers) all values is "sufficient"; i.e. the associated logical expression represents the desired function. For example, all minterms or maxterms are sufficient. However, the smallest set of prime implicants that covers all values forms a minimal expression for the desired function. There may be more than one minimal set.<br />
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<b><span style="color: red;">5 Variable K Maps</span></b><br />
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A five variable K Map can be constructed using two 4 variable maps side-by-side. The groups spanning both maps occupy the same place in both maps.<br />
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The above Figure is a map of:<br />
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When checking for adjacencies, each term should be checked against the five possible adjacent squares.</div>
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Karnaugh Map (or K-map) Minimization

The Karnaugh map provides a systematic method for simplifying a Boolean expression or a truth table function. The K map can produce the si...

Algebraic Minimization

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The goal of logic expression minimization is to find an equivalent of an original logic expression that has fewer variables per term, has fewer terms and needs less logic to implement. There are three main manual methods used for logic expression minimization; algebraic minimization, Karnaugh Map minimization and Quine-McCluskey (tabular) minimization</div>
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<b><span style="color: red;">Algebraic Minimization</span></b></div>
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The algebraic minimization process is the application of the switching algebra postulates, laws, and theorems to transform the original expression. It is hard to recognize when a particular law can be applied and difficult to know if resulting expression is truly minimal. The incorrect implementation or dropped variables etc can easy lead to a mistake.</div>
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The following are two examples of the algebraic minimization process by exploiting the adjacency theorem. Look for two terms that are identical except for one variable in the following expression</div>
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Application removes one term and one variable from the remaining term</div>
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In the following example one can look for the adjacency</div>
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The first and third term differ only A and <span style="font-family: 'Times New Roman', serif; font-size: 12pt; line-height: 115%;">Ᾱ</span><br />
The third and fourth term differ only A<sub><span style="font-family: "Times New Roman","serif"; font-size: 12.0pt; line-height: 115%; mso-ansi-language: EN-US; mso-bidi-language: AR-SA; mso-fareast-font-family: Calibri; mso-fareast-language: EN-US; mso-fareast-theme-font: minor-latin;">0</span></sub> and A<sub><span style="font-family: 'Times New Roman', serif; font-size: 12pt; line-height: 18.3999996185303px;">0</span></sub><br />
The second and third term differ only A<sub><span style="font-family: 'Times New Roman', serif; font-size: 12pt; line-height: 18.3999996185303px;">0</span></sub> and A<sub><span style="font-family: 'Times New Roman', serif; font-size: 12pt; line-height: 18.3999996185303px;">0</span></sub><br />
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Duplicate 3rd. term and rearrange<br />
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Apply adjacency on term pairs<br />
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Algebraic Minimization

The goal of logic expression minimization is to find an equivalent of an original logic expression that has fewer variables per term, has ...

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