NOR and NAND Architecture

NOR architecture is one of two technologies (the other being NAND) used in memory cards. NOR flash is the preferred technology for flash devices used to store and run code, usually in small capacities. NOR flash devices offer storage space up to 32-MB and while it has fast read capabilities it has slow write and slow erase functions compared to the NAND architecture. NOR technology is more commonly found as embedded designs and in lower-end set-top boxes and mobile handsets, and BIOS chips.

NOR flash architecture was introduced by Intel in 1988.

NAND Flash architecture is one of two flash technologies (the other being NOR) used in memory cards such as the CompactFlash cards. It is also used in USB Flash drives, MP3 players, and provides the image storage for digital cameras. NAND is best suited to flash devices requiring high capacity data storage. NAND flash devices offer storage space up to 512-MB and offers faster erase, write, and read capabilities over NOR architecture.

NAND flash architecture was introduced by Toshiba in 1989.

NOR ARCHITECTURE

Here every cell is connected in NOR fashioned manner as shown in Fig. 1.1(a). Note that the transistors used are FG type and two gates can be seen in their symbols. Every source terminal of the transistor is connected to ground in NOR architecture. Metal lines are required between each individual cell to run the ground in NOR architectures and therefore they occupy more area. NOR-based flash has long erase and write times, but has a full address/data (memory) interface that allows random access to any location. This makes it suitable for storage of program code that needs to be infrequently updated, such as computers' BIOS.

NAND ARCHITECTURE

In the NAND structure, a series of floating gate transistors are connected between the bit line and ground line. This organization allows the elimination of all contacts to ground line and thus reducing the area by 40% compared to NOR architecture. It has faster erase and write times, higher density, and lower cost per bit than NOR flash. This can be obtained by arranging 8 to 16 floating gate transistors connected in series as shown in the Fig. 1.1(b). However, its I/O interface allows only sequential to data. This makes it suitable for mass-storage devices such as PC cards and various memory stick cards.