Static Random Access Memory (SRAM) and Dynamic Random Access Memory (DRAM) are volatile memories. SRAM is used as a cache memory in computers since it offers the fastest write/read (~8ns) speed among all memories. Hardware design of a single SRAM cell consists of 6 transistors. A DRAM cell consists of one transistor and one capacitor and it is based on the charge stored in a capacitor. It is superior to SRAM because of its low cost per bit storage; nevertheless it is slower (`50ns). In DRAM, the stored charge in the capacitor can be maintained only for few milli-seconds and therefore, an extra hardware circuit is needed to periodically refresh the data periodically.
Static Random Access Memory (SRAM)
A single SRAM memory cell is shown in Figure below. Two NMOS and two PMOS transistors (M1 to M4) forms the simple latch to store the data and two pass NMOS transistors (M5 and M6) are controlled by Word Line to pass Bit Line and ~Bit Line into the cell.
A Write operation is performed by first charging the Bit Line and ~Bit Line with values that are desired to be stored in the memory cell. Setting the Word Line high performs the actual write operation, and the new data is latched into the circuit.
A Read operation is initiated by pre-charging both Bit Line and ~Bit Line to logic 1. Word Line is set high to close NMOS pass transistors to put the contents stored in the cell on the Bit Line and ~Bit Line.
Transistors M1 to M4 constitute the latch and are constantly toggling back and forth. During these switching the power consumption in CMOS circuits takes place and therefore, the sizes of these transistors are kept as small as possible. NMOS transistors are basically switches opening and closing access to the SRAM cell. To minimize the propagation delay caused by these transistors their sizes are kept relatively larger.
Dynamic Random Access Memory (DRAM)
DRAM stores each bit in a storage cell consisting of a capacitor and a transistor. Capacitors tend to lose their charge rather quickly; thus, the need for recharging. The presence or absence of charge in the capacitor determines whether the cell contains a '1' or a '0'. The Read operation begins by precharging the bit line to an intermediate value, VDD / 2. The word line is raised to a high potential and the charge stored on capacitor is shared with VDD / 2 that on the bit line. The change in the bit line voltage is given by the change on the bit line capacitor when the charge stored on capacitor C is shared with the bit line.
During the ' Write 1 ' operation, the word line is driven high, the bit line is tied to VDD corresponding to a 1, and voltage across C rises toward VDD - Vtn . To ' Write 0 ' in the cell, the bit line is grounded during the write operation and 0V is stored on capacitor C.
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