ECEstream: Intel 8051 Microcontroller

8051 Sample Assembly Language Programs

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<b><span style="color: #3d85c6;">Character transmission using a time delay</span></b></div>
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A program shown below takes the character in 'A' register, transmits it, delays for transmission time, and returns to the calling program. Timer-1 is used to set the baud rate, which is 1200 baud in this program.</div>
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The delay for one character transmission (in Mode 1 i.e.10 bits) is</div>
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10/2400 = 0.00833 seconds </div>
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Or, 8.33 milliseconds</div>
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Hence software delay of 10ms is used. </div>
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Timer-1 generates a baud rate close to 1200. Using a 12MHz crystal, the reload value is</div>
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Or, 230 i.e. E6H</div>
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This gives rise to an actual baud rate of 1202. </div>
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SMOD is programmed to be 0.</div>
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Assembly language Program is as follows:</div>
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; Code to wait for the transmission to complete</div>
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The subroutine TRMITTIME generates a delay of about 10ms. With a clock of 12MHz, one instruction cycle time is</div>
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The loop "MILSEC" generates a delay of about 1 x 10<sup><span style="font-family: "Times New Roman","serif"; font-size: 12.0pt; line-height: 115%; mso-ansi-language: EN-US; mso-bidi-language: AR-SA; mso-fareast-font-family: Calibri; mso-fareast-language: EN-US; mso-fareast-theme-font: minor-latin;">-3</span></sup> sec. This gets executed 10 times for a total delay of 10 x 10<sup><span style="font-family: "Times New Roman","serif"; font-size: 12.0pt; line-height: 115%; mso-ansi-language: EN-US; mso-bidi-language: AR-SA; mso-fareast-font-family: Calibri; mso-fareast-language: EN-US; mso-fareast-theme-font: minor-latin;">-3</span></sup> sec or 10ms</div>
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<b><span style="color: #3d85c6;">Interrupt driven character transmission</span></b></div>
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In 8051, when a character is transmitted, SBUF register becomes empty and this generates a serial port interrupt (TI). TI and RI both point to the vector location 0023H in the program memory. An interrupt service routine can be written at 0023H to send the next character.</div>
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A program is written here to transmit a character say 'A' continuously based on interrupt. The microcontroller uses a clock of 12MHz with a baud rate of 1202. The program is executed following a hardware reset.</div>
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Assembly language program is as follows.</div>
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<b><span style="color: #3d85c6;">Interrupt driven data reception</span></b></div>
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When a character is received, if receive mode is enabled, RI flag is set. This leads to the interruption of the main program and the processor goes to the interrupt vector location, i.e. 0023H for serial port. The interrupt service routine at 0023H gets executed to read the character so that the next character can be received. The following program receives a character on interrupt basis and outputs the character to port-1, possibly for a display.</div>
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The crystal frequency is12MHz and baud rate is set at 1202 baud.</div>
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Assembly language program is as follows:</div>
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8051 Sample Assembly Language Programs

Character transmission using a time delay A program shown below takes the character in 'A' register, transmits it, delays for ...

Serial Communication in 8051

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<b>Serial Interface</b></div>
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The serial port of 8051 is full duplex, i.e., it can transmit and receive simultaneously.</div>
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The register SBUF is used to hold the data. The special function register SBUF is physically two registers. One is, write-only and is used to hold data to be transmitted out of the 8051 via TXD. The other is, read-only and holds the received data from external sources via RXD. Both mutually exclusive registers have the same address 099H.</div>
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<b>Serial Port Control Register (SCON)</b></div>
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Register SCON controls serial data communication. </div>
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Address: 098H (Bit addressable)</div>
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<img alt="SCON Register" border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjs9u0zaqp76ba37jMHe-lHizdQH7LT18Qw2jpgcjWPlaVN2SrDGldJVLhNPb9SA3YDVOsYRDYKJiey-p1CiqA8cCwH9H1BhoWLEfnT4xTcq3kXgDoToriA1qs1ZqUQNEYbawrdTxvCdB3k/s1600/SCON.png" title="SCON Register" /></div>
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Mode select bits</div>
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<img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhCgcXphUCsNp6woEMPIHhUpuHGmxMnun8jzzJ6ozDb3xqqrC6uUlMNX2kFmCx83dzrzKHtqk_rMctWeeyHLbEdDe9sZfv9GjBejXhsy8q_RQdPFTroKiA_AS1WCDwTj7uTwViJzV0MAnWP/s1600/table.png" /></div>
SM2: multi processor communication bit </div>
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REN: Receive enable bit </div>
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TB8: Transmitted bit 8 (Normally we have 0-7 bits transmitted/received) </div>
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RB8: Received bit 8 </div>
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TI: Transmit interrupt flag </div>
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RI: Receive interrupt flag</div>
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<b>Power Mode control Register</b></div>
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Register PCON controls processor powerdown, sleep modes and serial data bandrate. Only one bit of PCON is used with respect to serial communication. The seventh bit (b7)(SMOD) is used to generate the baud rate of serial communication.</div>
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Address: 87H</div>
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<img alt="PCON Register" border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEh_9Dk8OQgfuZo8EeoCSwCaTEEO5PJkUxojeEhVrvsGtumvea7GYQ9Up60RIOnbV_d2zOtj-8w2f2sAr70GsSat-U4LPAfdy-9iK05D0FpoLavhSGok_xOkYmS0VJy6HxqD32HDLvEMqVnQ/s1600/pcon.png" title="PCON Register" /></div>
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SMOD: Serial baud rate modify bit </div>
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GF1: General purpose user flag bit 1 </div>
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GF0: General purpose user flag bit 0 </div>
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PD: Power down bit </div>
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IDL: Idle mode bit</div>
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<b>Data Transmission</b></div>
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Transmission of serial data begins at any time when data is written to SBUF. Pin P3.1 (Alternate function bit TXD) is used to transmit data to the serial data network. TI is set to 1 when data has been transmitted. This signifies that SBUF is empty so that another byte can be sent.</div>
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<b>Data Reception</b></div>
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Reception of serial data begins if the receive enable bit is set to 1 for all modes. Pin P3.0 (Alternate function bit RXD) is used to receive data from the serial data network. Receive interrupt flag, RI, is set after the data has been received in all modes. The data gets stored in SBUF register from where it can be read.</div>
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<b>Serial Data Transmission Modes:</b></div>
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<b>Mode-0</b>: In this mode, the serial port works like a shift register and the data transmission works synchronously with a clock frequency of fosc /12. Serial data is received and transmitted through RXD. 8 bits are transmitted/ received aty a time. Pin TXD outputs the shift clock pulses of frequency fosc /12, which is connected to the external circuitry for synchronization. The shift frequency or baud rate is always 1/12 of the oscillator frequency.<br />
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<img alt="Serial Data transmission in Mode-0" border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhMZtUAegrngyxuNjXN3-K-yiR1COtqvUHj3GIBMBKq5PKWqQtQ4SIIuDNVNC8-fNrAXi6B-94uWoaM5IIcMFoN_g4vnWMDgx9dowi2jBh7bQgbRpSfwO9QC27NRIrL7FgcP_B0FPoDTES2/s1600/Data+transmission+&+reception+in+Mode-0.png" title="Serial Data transmission in Mode-0" /></div>
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<b><i>Fig 1. Data transmission/reception in Mode-0</i></b></div>
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<b>Mode-1 (standard UART mode) : </b>In mode-1, the serial port functions as a standard Universal Asynchronous Receiver Transmitter (UART) mode. 10 bits are transmitted through TXD or received through RXD. The 10 bits consist of one start bit (which is usually '0'), 8 data bits (LSB is sent first/received first), and a stop bit (which is usually '1'). Once received, the stop bit goes into RB8 in the special function register SCON. The baud rate is variable.<br />
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The following figure shows the way the bits are transmitted/ received.<br />
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<img alt="Data transmission format in UART mode" border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEi8il1OSngWn7MTzPgdmDqxROt72vGw_JTtma4uA1dB8VNYOko1BxNoXGkWfsTScMAqHT9ZVAdymtI9KzYsOprHVFpJtd0xAkicXEddwCu31zHnD-p4gTQW2Mws-7TdvBx4etPc84LyJL9q/s1600/Data+transmission+format+in+UART+mode.png" title="Data transmission format in UART mode" /></div>
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<b><i>Fig 2. Data transmission format in UART mode</i></b></div>
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Bit time = 1/<span style="font-family: Calibri, sans-serif; font-size: 13.5pt; line-height: 115%;">f</span><sub style="font-family: Calibri, sans-serif; line-height: 115%;">baud</sub><br />
In receiving mode, data bits are shifted into the receiver at the programmed baud rate. The data word (8-bits) will be loaded to SBUF if the following conditions are true.<br />
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<li>RI must be zero. (i.e., the previously received byte has been cleared from SBUF)</li>
<li>Mode bit SM2 = 0 or stop bit = 1.</li>
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After the data is received and the data byte has been loaded into SBUF, RI becomes one.<br />
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<b>Mode-1 baud rate generation: </b>Timer-1 is used to generate baud rate for mode-1 serial communication by using overflow flag of the timer to determine the baud frequency. Timer-1 is used in timer mode-2 as an auto-reload 8-bit timer. The data rate is generated by timer-1 using the following formula.<br />
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<img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgnwFtozomW5aOPLGhZwJf_rYVqAQcvA9upe6gWiWBsfOKCwwJzODx8nR2tDW39KjmP7zKeUgldxByIO5laLgePRl36iAyRh91SMqlWkA8kNHbFtI6kNtsbhyRu4qW46LaooTS2mACTsj9H/s1600/baud+rate.png" /></div>
Where;<br />
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SMOD is the 7th bit of PCON register </div>
<span style="font-family: Calibri, sans-serif; font-size: 13.5pt; line-height: 20.7000007629395px;">f</span><sub style="font-family: Calibri, sans-serif; line-height: 15.3333320617676px;">osc</sub> is the crystal oscillator frequency of the microcontroller<br />
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It can be noted that <span style="font-family: Calibri, sans-serif; font-size: 13.5pt; line-height: 20.7000007629395px;">f</span><sub style="font-family: Calibri, sans-serif; line-height: 15.3333320617676px;">osc</sub>/ (12 X [256- (TH1)]) is the timer overflow frequency in timer mode-2, which is the auto-reload mode.<br />
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If timer-1 is not run in mode-2, then the baud rate is,<br />
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<img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgq_OhjtGoeYLfQT_8wMzSwUp6G8Ty60PmdkmTa2XfPbsT8esY9Axu2e692Ov3rhFWoVO0gtsamGzpiqzdHPsID4cCcEFQHWglCP14RP78-BuQNHAa_Pi3uFHpV-pmWnyypk3QlszRJm4E-/s1600/baud+rate1.png" /></div>
Timer-1 can be run using the internal clock, <span style="font-family: Calibri, sans-serif; font-size: 13.5pt; line-height: 20.7000007629395px;">f</span><sub style="font-family: Calibri, sans-serif; line-height: 15.3333320617676px;">osc</sub>/12 (timer mode) or from any external source via pin T1 (P3.5) (Counter mode).<br />
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<b>Example</b>: If standard baud rate is desired, then 11.0592 MHz crystal could be selected. To get a standard 9600 baud rate, the setting of TH1 is calculated as follows.<br />
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Assuming SMOD to be '0'<br />
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Or,<br />
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<img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgBSz_CdxyTgdzvQmVJf28hSea0qibvTMFoVUn1mBoT-JvfYRuXTjtfey_C9T9VvO1BGWHG-7btbbpcBRj_CNkHi6PYRwbC1d_OhbASpH3IFOLyfitq2JPG9FrNEtloPrlpRUBxAlg-wwbS/s1600/eg2.png" /></div>
Or,<br />
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TH1 = 256 - 3 = 253 = FDH</div>
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In mode-1, if SM2 is set to 1, no receive interrupt (RI) is generated unless a valid stop bit is received.<br />
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<b>Serial Data Mode-2 - Multiprocessor Mode :</b><br />
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In this mode 11 bits are transmitted through TXD or received through RXD. The various bits are as follows: a start bit (usually '0'), 8 data bits (LSB first), a programmable 9 th (TB8 or RB8)bit and a stop bit (usually '1').<br />
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While transmitting, the 9 th data bit (TB8 in SCON) can be assigned the value '0' or '1'. For example, if the information of parity is to be transmitted, the parity bit (P) in PSW could be moved into TB8. On reception of the data, the 9 th bit goes into RB8 in 'SCON', while the stop bit is ignored. The baud rate is programmable to either 1/32 or 1/64 of the oscillator frequency.<br />
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<span style="font-family: Calibri, sans-serif; font-size: 13.5pt; line-height: 20.7000007629395px;">f</span><sub style="font-family: Calibri, sans-serif; line-height: 15.3333320617676px;">baud</sub> = (<span style="font-family: Calibri, sans-serif; font-size: 13.5pt; line-height: 115%;">2<sup>SMOD</sup></span> /64) <span style="font-family: Calibri, sans-serif; font-size: 13.5pt; line-height: 20.7000007629395px;">f</span><sub style="font-family: Calibri, sans-serif; line-height: 15.3333320617676px;">osc</sub>.</div>
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<b>Mode-3 - Multi processor mode with variable baud rate :</b><br />
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In this mode 11 bits are transmitted through TXD or received through RXD. The various bits are: a start bit (usually '0'), 8 data bits (LSB first), a programmable 9th bit and a stop bit (usually '1').<br />
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Mode-3 is same as mode-2, except the fact that the baud rate in mode-3 is variable (i.e., just as in mode-1).<br />
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<span style="font-family: Calibri, sans-serif; font-size: 13.5pt; line-height: 20.7000007629395px; text-align: center;">f</span><sub style="font-family: Calibri, sans-serif; line-height: 15.3333320617676px; text-align: center;">baud</sub> = (<span style="font-family: Calibri, sans-serif; font-size: 18px; line-height: 20.7000007629395px; text-align: center;">2</span><sup style="font-family: Calibri, sans-serif; line-height: 20.7000007629395px; text-align: center;">SMOD</sup> /32) * ( <span style="font-family: Calibri, sans-serif; font-size: 13.5pt; line-height: 20.7000007629395px; text-align: center;">f</span><sub style="font-family: Calibri, sans-serif; line-height: 15.3333320617676px; text-align: center;">osc</sub> / 12 (256-TH1)) .<br />
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This baud rate  holds when Timer-1 is programmed in Mode-2.<br />
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<b>Operation in Multiprocessor mode :</b><br />
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8051 operates in multiprocessor mode for serial communication Mode-2 and Mode-3. In multiprocessor mode, a Master processor can communicate with more than one slave processors. The connection diagram of processors communicating in Multiprocessor mode is given in fig 3.<br />
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The Master communicates with one slave at a time. 11 bits are transmitted by the Master, viz, One start bit (usually '0'), 8 data bits (LSB first), TB8 and a stop bit (usually '1'). TB8 is '1' for an address byte and '0' for a data byte.<br />
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If the Master wants to communicate with certain slave, it first sends the address of the slave with TB8=1. This address is received by all the slaves. Slaves initially have their SM2 bit set to '1'. All slaves check this address and the slave who is being addressed, responds by clearing its SM2 bit to '0' so that the data bytes can be received.<br />
It should be noted that in Mode 2&3, receive interrupt flag RI is set if REN=1, RI=0 and the following condition is true.<br />
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<li>SM2=1 and RB8=1 and a valid stop bit is received. Or</li>
<li>SM2=0 and a valid stop bit is received.</li>
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<img alt="8051 in Multiprocessor Communication" border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEiQXBvFiLQYOXW5Wsrq9H1x6yTSXqN7c6ZrLGhDRcJUZi-5K5fxNpHOVTIsDx9hPHiEQLQDEpHLCkzyW8e7BISkYmx8L2JATUmf7G5uko6dJLo7885S9hNfdcbS_IR4Qe2x-SNTjYBoalxn/s1600/8051++in+Multiprocessor+Communication.png" title="8051 in Multiprocessor Communication" /></div>
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<b><i>Fig 3. 8051 in Multiprocessor Communication</i></b></div>
<br />
After the communication between the Master and a slave has been established, the data bytes are sent by the Master with TB8=0. Hence other slaves do not respond /get interrupted by this data as their SM2 is pulled high (1).<br />
<br />
<b>Power saving modes of operation :</b><br />
<br />
8051 has two power saving modes. They are -<br />
<ul>
<li>Idle Mode</li>
<li>Power Down mode.</li>
</ul>
The two power saving modes are entered by setting two bits IDL and PD in the special function register (PCON) respectively.<br />
<br />
The structure of PCON register is as follows.<br />
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<img alt="structure of PCON register" border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEiDebwFVsf2ilhIIfx_8tMiwdaAdEmQ4dd_-YleKlUUfb9u-YMT4d7SYkRFBABrZLzYbAOdTOBmCbwwUMslfQFLGVRRZiBsgeKVnXa82b-EpmAeMiv_Lp1r49UBQYrJWlqBzfUpJ331Pw2m/s1600/SMOD.png" title="structure of PCON register" /></div>
The schematic diagram for 'Power down' mode and 'Idle' mode is given as follows:<br />
<br />
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<img alt="Power Down and Idle mode implementation" border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgPBa9E6zAOpqO2sGtHXP7v1lZXICvDMzqtVgNbuVf406LA2RK7VDjJnSlq-4maMEiwYWPSNYQbaZgLsRxqIqMbfejORmaCNx2kmBb_bmY9FGam_C0775RLQwTXXbZIMdgS5sltLJVrmlH9/s1600/Schematic+diagram+for+Power+Down+and+Idle+mode+implementation.png" title="Power Down and Idle mode implementation" /></div>
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<b><i>Fig 4. Schematic diagram for Power Down and Idle mode implementation</i></b></div>
<br />
<b>Idle Mode</b><br />
<br />
Idle mode is entered by setting IDL bit to 1 (i.e., <span style="font-size: 13.5pt; line-height: 115%;"><span style="font-family: inherit;">~</span></span>IDL = 0). The clock signal is gated off to CPU, but not to the interrupt, timer and serial port functions. The CPU status is preserved entirely. SP, PC, PSW, Accumulator and other registers maintain their data during IDLE mode. The port pins hold their logical states they had at the time Idle was initiated. ALE and <span style="font-size: 13.5pt; line-height: 115%;"><span style="font-family: inherit;">~</span></span>PSEN are held at logic high levels.<br />
<br />
<b>Ways to exit Idle Mode:</b><br />
<ol>
<li>Activation of any enabled interrupt will clear PCON.0 bit and hence the Idle Mode is exited. The program goes to the Interrupt Service Routine (ISR). After RETI is executed at the end of the ISR, the next instruction will start from the one following the instruction that enabled Idle Mode.</li>
<li>A hardware reset exits the idle mode. The CPU starts from the instruction following the instruction that invoked the 'Idle' mode.</li>
</ol>
<div>
<b>Power Down Mode:</b></div>
<div>
<br /></div>
<div>
The Power down Mode is entered by setting the PD bit to  1. The internal clock to the entire microcontroller is stopped (frozen). However, the program is not dead. The Power down Mode is exited (PCON.1 is cleared to 0) by Hardware Reset only. The CPU starts from the next instruction where the Power down Mode was invoked. Port values are not changed/ overwritten in power down mode. <span style="font-family: Calibri, sans-serif; font-size: 13.5pt; line-height: 20.7000007629395px; text-align: center;">V</span><sub style="font-family: Calibri, sans-serif; line-height: 15.3333320617676px; text-align: center;">cc</sub> can be reduced to as low as 2V in Power Down mode. However, Vcc  has to be restored to normal value before Power Down mode is exited.</div>
</div>
</div>

Serial Communication in 8051

Serial Interface The serial port of 8051 is full duplex, i.e., it can transmit and receive simultaneously. The register SBUF is us...

Program Branching Instructions in 8051

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<b>Jump and Call Instructions</b></div>
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There are 3 types of jump instructions. They are:-</div>
<div style="text-align: justify;">
</div>
<ol>
<li>Relative Jump</li>
<li>Short Absolute Jump</li>
<li>Long Absolute Jump</li>
</ol>
<b>Relative Jump</b><br />
<br />
<div style="text-align: justify;">
Jump that replaces the PC (program counter) content with a new address that is greater than (the address following the jump instruction by 127 or less) or less than (the address following the jump by 128 or less) is called a relative jump. Schematically, the relative jump can be shown as follows:</div>
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<br /></div>
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<img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEioTWUMzpavbwPYPTYThTp2vuzqpwoGcE2BhCkyqNAKoTYuZsYyXRTfQDnbdwGYeqpi0aG70mfKqCqdlOeuQpqQ2GLZQyiWUuZLfS5BJCH6daWb3Lb2r812z5_jWS4tw9vHtqx9SMIpSs9w/s1600/Relative+Jump.png" /></div>
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<b><i>Fig 1. Relative Jump</i></b></div>
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<br /></div>
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The advantages of the relative jump are as follows:</div>
<div style="text-align: justify;">
</div>
<ol>
<li>Only 1 byte of jump address needs to be specified in the 2's complement form, ie. For jumping ahead, the range is 0 to 127 and for jumping back, the range is -1 to -128.</li>
<li>Specifying only one byte reduces the size of the instruction and speeds up program execution.</li>
<li>The program with relative jumps can be relocated without reassembling to generate absolute jump addresses.</li>
</ol>
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Disadvantages of the absolute jump:</div>
<div style="text-align: justify;">
</div>
<ol>
<li>Short jump range (-128 to 127 from the instruction following the jump instruction)</li>
</ol>
<br />
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<b>Instructions that use Relative Jump</b></div>
<div style="text-align: justify;">
SJMP <relative address> </div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
(The remaining relative jumps are conditional jumps)</div>
<div style="text-align: justify;">
JC <relative address> </div>
<div style="text-align: justify;">
JNC <relative address></div>
<div style="text-align: justify;">
JB bit, <relative address></div>
<div style="text-align: justify;">
JNB bit, <relative address></div>
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JBC bit, <relative address></div>
<div style="text-align: justify;">
CJNE <destination byte>, <source byte>, <relative address></div>
<div style="text-align: justify;">
DJNZ <byte>, <relative address></div>
<div style="text-align: justify;">
JZ <relative address></div>
<div style="text-align: justify;">
JNZ <relative address></div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
<b>Short Absolute Jump</b></div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
In this case only 11bits of the absolute jump address are needed. The absolute jump address is calculated in the following manner. </div>
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In 8051, 64 kbyte of program memory space is divided into 32 pages of 2 kbyte each. The hexadecimal addresses of the pages are given as follows:</div>
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<tr class="BodyText" style="font-size: 12px; text-align: justify;"><td valign="top" width="79"><div align="center" class="SubHeading" style="color: #5e52a5; font-weight: bold;">
<strong>Page (Hex)</strong></div>
</td><td valign="top" width="173"><div align="center" class="SubHeading" style="color: #5e52a5; font-weight: bold;">
<strong>Address (Hex)</strong></div>
</td></tr>
<tr class="BodyText" style="font-size: 12px; text-align: justify;"><td valign="top" width="79"><div align="center">
00</div>
</td><td valign="top" width="173"><div align="center">
0000 - 07FF</div>
</td></tr>
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01</div>
</td><td valign="top" width="173"><div align="center">
0800 - 0FFF</div>
</td></tr>
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02</div>
</td><td valign="top" width="173"><div align="center">
1000 - 17FF</div>
</td></tr>
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03</div>
</td><td valign="top" width="173"><div align="center">
1800 - 1FFF</div>
</td></tr>
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.</div>
</td><td valign="top" width="173"><div align="center">
.</div>
</td></tr>
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1E</div>
</td><td valign="top" width="173"><div align="center">
F000 - F7FF</div>
</td></tr>
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1F</div>
</td><td valign="top" width="173"><div align="center">
F800 - FFFF</div>
</td></tr>
</tbody></table>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
It can be seen that the upper 5bits of the program counter(PC) hold the page number and the lower 11bits of the PC hold the address within that page. Thus, an absolute address is formed by taking page numbers of the instruction (from the program counter) following the jump and attaching the specified 11bits to it to form the 16-bit address.</div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
<u>Advantage</u>: The instruction length becomes 2 bytes.</div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
However, difficulty is encountered when the next instruction following the jump instruction begins from a fresh page (at X000H or at X800H). This does not give any problem for the forward jump, but results in an error for the backward jump. In such a case the assembler prompts the user to relocate the program suitably.</div>
<div style="text-align: justify;">
Example of short absolute jump:</div>
<div style="text-align: justify;">
ACALL <address 11> </div>
<div style="text-align: justify;">
AJMP   <address 11></div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
<b>Long Absolute Jump/Call</b></div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
Applications that need to access the entire program memory from 0000H to FFFFH use long absolute jump. Since the absolute address has to be specified in the op-code, the instruction length is 3 bytes (except for JMP @ A+DPTR). This jump is not re-locatable.</div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
Example:</div>
<div style="text-align: justify;">
LCALL <address 16> </div>
<div style="text-align: justify;">
LJMP    <address 16></div>
<div style="text-align: justify;">
JMP @A+DPTR</div>
</div>

Program Branching Instructions in 8051

Jump and Call Instructions There are 3 types of jump instructions. They are:- Relative Jump Short Absolute Jump Long Absolute Jump...

Interrupts in 8051

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<b>Interrupts</b></div>
<div style="text-align: justify;">
8051 provides 5 vectored interrupts. They are -</div>
<div style="text-align: justify;">
<ol>
<li><span style="font-family: "Calibri","sans-serif"; font-size: 12.0pt; line-height: 115%; mso-ansi-language: EN-US; mso-ascii-theme-font: minor-latin; mso-bidi-font-family: "Times New Roman"; mso-bidi-language: AR-SA; mso-bidi-theme-font: minor-bidi; mso-fareast-font-family: Calibri; mso-fareast-language: EN-US; mso-fareast-theme-font: minor-latin; mso-hansi-theme-font: minor-latin;">~</span>INT0</li>
<li>TF0</li>
<li><span style="font-family: "Calibri","sans-serif"; font-size: 12.0pt; line-height: 115%; mso-ansi-language: EN-US; mso-ascii-theme-font: minor-latin; mso-bidi-font-family: "Times New Roman"; mso-bidi-language: AR-SA; mso-bidi-theme-font: minor-bidi; mso-fareast-font-family: Calibri; mso-fareast-language: EN-US; mso-fareast-theme-font: minor-latin; mso-hansi-theme-font: minor-latin;">~</span>INT1</li>
<li>TF1</li>
<li>RI/TI</li>
</ol>
</div>
<div>
<div style="text-align: justify;">
Out of these, <span style="font-size: 13.5pt; line-height: 115%;"><span style="font-family: inherit;">~</span></span>INT0 and <span style="font-size: 13.5pt; line-height: 115%;"><span style="font-family: inherit;">~</span></span>INT1 are external interrupts whereas Timer and Serial port interrupts are generated internally. The external interrupts could be negative edge triggered or low level triggered. All these interrupt, when activated, set the corresponding interrupt flags. Except for serial interrupt, the interrupt flags are cleared when the processor branches to the Interrupt Service Routine (ISR). The external interrupt flags are cleared on branching to Interrupt Service Routine (ISR), provided the interrupt is negative edge triggered. For low level triggered external interrupt as well as for serial interrupt, the corresponding flags have to be cleared by software by the programmer.</div>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
The schematic representation of the interrupts is as follows -<br />
<br />
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<img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEiMUKeJ-Rx8xuzB-kLBR7H5qyaBITGmZFSC0ZDOekEKwANeTWbxXfA4eSelnsOUntxT1gNt1vmuaDrSyKAHCV9q3RhGlKzYtvAhp_LTBTd06JkOc4-PSqj_FAKWdCfP3tZpNE9EyjZeMwEd/s1600/8051+Interrupt+Details.png" /></div>
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<b><i>Fig 1. 8051 Interrupt Details</i></b></div>
<br />
Each of these interrupts can be individually enabled or disabled by 'setting' or 'clearing' the corresponding bit in the IE (Interrupt Enable Register) SFR. IE contains a global enable bit EA which enables/disables all interrupts at once.<br />
<br />
<b>Interrupt Enable register (IE):</b><br />
<br />
Address: A8H<br />
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<img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEicS6eYfhsYYJy9KNhEFScN8BK6TzzO0GQlxaEuT-VpviZWr8Ps-CO3VZSVXYqdJcVW3r2KIfkjS_RaYlzU9i7M5d0o2KZQNCnqghso_T3iwxrTo4eaqq9xftKcI_BaO7X1ei0U476K6M6a/s1600/IE.png" /></div>
<br />
<u>EX0</u>: INT0 interrupt (External) enable bit<br />
<u>ET0</u>: Timer-0 interrupt enable bit<br />
<u>EX1</u>: INT1 interrupt (External) enable bit<br />
<u>ET1</u>: Timer-1 interrupt enable bit<br />
<u>ES</u>: Serial port interrupt enable bit<br />
<u>ET2</u>: Timer-2 interrupt enable bit<br />
<u>EA</u>: Enable/Disable all<br />
<u>Setting '1'</u>: Enable the corresponding interrupt<br />
<u>Setting '0'</u>: Disable the corresponding interrupt<br />
<br />
<b>Priority level structure:</b><br />
<br />
Each interrupt source can be programmed to have one of the two priority levels by setting (high priority) or clearing (low priority) a bit in the IP (Interrupt Priority) Register . A low priority interrupt can itself be interrupted by a high priority interrupt, but not by another low priority interrupt. If two interrupts of different priority levels are received simultaneously, the request of higher priority level is served. If the requests of the same priority level are received simultaneously, an internal polling sequence determines which request is to be serviced. Thus, within each priority level, there is a second priority level determined by the polling sequence, as follows.<br />
<br />
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<img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEitBf456L2RBvWLvUUCotyzzlylWDhb__6ASt5GYujbrVV4QuaCXH0mslyVCCA0SoccXHvh8zPRHhVE53YBDBUNZvgd09A4xNaXLtyjIdndNrs4cHQCn-_LxDksd3melYQodqL0t-Akwomj/s1600/Priority.png" /></div>
<br />
<b>Interrupt Priority register  (IP)</b><br />
<br />
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<img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEj9XijfGCL2z6GesCRB7kMplVA7I4QDtfag7Qc9iqjre7z9vzser9wW2ijKJRdd6FhEblIBHocfsV6f3XD8ImD8vaYGtFxSsMSrge7opFS8e_vCHXyxz-8FhyL-R2G8xYlg2KUFhaB1IwqF/s1600/iP.png" /></div>
'0' - low priority<br />
'1' - high priority<br />
<br />
<b>Interrupt handling:</b><br />
<br />
The interrupt flags are sampled at P2 of S5 of every instruction cycle (Note that every instruction cycle has six states each consisting of P1 and P2 pulses). The samples are polled during the next machine cycle (or instruction cycle). If one of the flags was set at S5P2 of the preceding instruction cycle, the polling detects it and the interrupt process generates a long call (LCALL) to the appropriate vector location of the interrupt. The LCALL is generated provided this hardware generated LCALL is not blocked by any one of the following conditions.<br />
<ol>
<li>An interrupt of equal or higher priority level is already in progress.</li>
<li>The current polling cycle is not the final cycle in the execution of the instruction in progress.</li>
<li>The instruction in progress is RETI or any write to IE or IP registers.</li>
</ol>
When an interrupt comes and the program is directed to the interrupt vector address, the Program Counter (PC) value of the interrupted program is stored (pushed) on the stack. The required Interrupt Service Routine (ISR) is executed. At the end of the ISR, the instruction RETI returns the value of the PC from the stack and the originally interrupted program is resumed.<br />
<br />
<u>Reset</u> is a non-maskable interrupt. A reset is accomplished by holding the RST pin high for at least two machine cycles. On resetting the program starts from 0000H and some flags are modified as follows -<br />
<br />
<table align="center" border="1" cellpadding="1" style="background-color: #e3eaf6; font-family: Arial, Helvetica, sans-serif; width: 274px;"><tbody>
<tr class="SubHeading" style="color: #5e52a5; font-size: 12px; font-weight: bold;"><th scope="col"><div align="center">
Register</div>
</th><th scope="col">Value(Hex) on Reset</th></tr>
<tr class="BodyText" style="font-size: 12px; text-align: justify;"><td><div align="center">
PC</div>
</td><td><div align="center">
0000H</div>
</td></tr>
<tr class="BodyText" style="font-size: 12px; text-align: justify;"><td><div align="center">
DPTR</div>
</td><td><div align="center">
0000H</div>
</td></tr>
<tr class="BodyText" style="font-size: 12px; text-align: justify;"><td><div align="center">
A</div>
</td><td><div align="center">
00H</div>
</td></tr>
<tr class="BodyText" style="font-size: 12px; text-align: justify;"><td><div align="center">
B</div>
</td><td><div align="center">
00H</div>
</td></tr>
<tr class="BodyText" style="font-size: 12px; text-align: justify;"><td><div align="center">
SP</div>
</td><td><div align="center">
07H</div>
</td></tr>
<tr class="BodyText" style="font-size: 12px; text-align: justify;"><td><div align="center">
PSW</div>
</td><td><div align="center">
00H</div>
</td></tr>
<tr class="BodyText" style="font-size: 12px; text-align: justify;"><td><div align="center">
Ports P0-3 Latches</div>
</td><td><div align="center">
FFH</div>
</td></tr>
<tr class="BodyText" style="font-size: 12px; text-align: justify;"><td><div align="center">
IP</div>
</td><td><div align="center">
XXX 00000 b</div>
</td></tr>
<tr class="BodyText" style="font-size: 12px; text-align: justify;"><td><div align="center">
IE</div>
</td><td><div align="center">
0 XX 00000 b</div>
</td></tr>
<tr class="BodyText" style="font-size: 12px; text-align: justify;"><td><div align="center">
TCON</div>
</td><td><div align="center">
00H</div>
</td></tr>
<tr class="BodyText" style="font-size: 12px; text-align: justify;"><td><div align="center">
TMOD</div>
</td><td><div align="center">
00H</div>
</td></tr>
<tr class="BodyText" style="font-size: 12px; text-align: justify;"><td><div align="center">
TH0</div>
</td><td><div align="center">
00H</div>
</td></tr>
<tr class="BodyText" style="font-size: 12px; text-align: justify;"><td><div align="center">
TL0</div>
</td><td><div align="center">
00H</div>
</td></tr>
<tr class="BodyText" style="font-size: 12px; text-align: justify;"><td><div align="center">
TH1</div>
</td><td><div align="center">
00H</div>
</td></tr>
<tr class="BodyText" style="font-size: 12px; text-align: justify;"><td><div align="center">
TL1</div>
</td><td><div align="center">
00H</div>
</td></tr>
<tr class="BodyText" style="font-size: 12px; text-align: justify;"><td><div align="center">
SCON</div>
</td><td><div align="center">
00H</div>
</td></tr>
<tr class="BodyText" style="font-size: 12px; text-align: justify;"><td><div align="center">
SBUF</div>
</td><td><div align="center">
XX H</div>
</td></tr>
<tr class="BodyText" style="font-size: 12px; text-align: justify;"><td><div align="center">
PCON</div>
</td><td><div align="center">
0  XXXX XXX  b</div>
</td></tr>
</tbody></table>
<br />
The schematic diagram of the detection and processing of interrupts is given as follows.<br />
<br />
Instruction Cycles -<br />
<br />
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<img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEg8kuQp9SGCk4Asrbt_Kht8lI2jxO59A22AbF2ulEhnxtd5yU2YwQBwbiyCpe-fPLfSAdy9UOg-g3Gaq-g-SKr8CXLwFT54pZVbC6wWE3SDxzhrVXc70_JxLKy9OEgp_VMFSInytMzjP8vm/s1600/Interrupt+Handling+in+8051.png" /></div>
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<b><i>Fig 2. Interrupt Handling in 8051</i></b></div>
<br />
It should be noted that the interrupt which is blocked due to the three conditions mentioned before is not remembered unless the flag that generated interrupt is not still active when the above blocking conditions are removed, i.e. ,every polling cycle is new.</div>
</div>
</div>

Interrupts in 8051

Interrupts 8051 provides 5 vectored interrupts. They are - ~ INT0 TF0 ~ INT1 TF1 RI/TI Out of these, ~ INT0 and ~ INT1 are...

Timers / Counters in 8051

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<b>Timers / Counters</b></div>
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8051 has two 16-bit programmable UP timers/counters. They can be configured to operate either as timers or as event counters. The names of the two counters are T0 and T1 respectively.  The timer content is available in four 8-bit special function registers, viz, TL0,TH0,TL1 and TH1 respectively.</div>
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In the "timer" function mode, the counter is incremented in every machine cycle. Thus, one can think of it as counting machine cycles. Hence the clock rate is 1/12 th of the oscillator frequency.</div>
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In the "counter" function mode, the register is incremented in response to a 1 to 0 transition at its corresponding external input pin (T0 or T1). It requires 2 machine cycles to detect a high to low transition. Hence maximum count rate is 1/24 th of oscillator frequency.</div>
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The operation of the timers/counters is controlled by two special function registers, TMOD and TCON respectively.</div>
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<b>Timer Mode control (TMOD) Special Function Register:</b></div>
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TMOD register is not bit addressable.</div>
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TMOD</div>
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Address: 89 H</div>
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<img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhrpGZrEXz3e6UU-kFS5YjOzler7bAmwTaMiLhl6gviNTXBcndRzmBsbontWg-9qssjdhEvKEy8xvSrnqABGB8nlQdzLT5uxQd-VqJY6hsrv16ELykHEPkN-V2v7rWdPgrjCjcI4RO82YaE/s1600/TMOD.png" /></div>
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Various bits  of TMOD are described as follows -</div>
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<b>Gate</b>: This is an OR Gate enabled bit which controls the effect of <span style="font-family: Calibri, sans-serif; font-size: 12pt; line-height: 115%;">~</span>INT1/0 on START/STOP of Timer. It is set to one ('1') by the program to enable the interrupt to start/stop the timer. If TR1/0 in TCON is set and signal on <span style="font-family: Calibri, sans-serif; font-size: 12pt; line-height: 115%;">~</span>INT1/0 pin is high then the timer starts counting using either internal clock (timer mode) or external pulses (counter mode).</div>
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<b>C/<span style="font-family: Calibri, sans-serif; font-size: 12pt; line-height: 115%;">~</span>T</b>: It is used for the selection of Counter/Timer mode. </div>
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Mode Select Bits:</div>
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M1 and M0 are mode select bits.</div>
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<b>Timer/ Counter control logic:</b></div>
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<b><i>Fig 1. Timer/Counter Control Logic</i></b></div>
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<b>Timer control (TCON) Special function register:</b></div>
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TCON is bit addressable. The address of TCON is 88H. It is partly related to Timer and partly to interrupt.</div>
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<b><i>Fig 2. TCON Register</i></b></div>
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The various bits of TCON are as follows.</div>
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<u>TF1</u>: Timer1 overflow flag. It is set when timer rolls from all 1s to 0s. It is cleared when processor vectors to execute ISR located at address 001BH. </div>
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<u>TR1</u>: Timer1 run control bit. Set to 1 to start the timer / counter. </div>
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<u>TF0</u>: Timer0 overflow flag. (Similar to TF1)</div>
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<u>TR0</u>: Timer0 run control bit. </div>
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<u>IE1</u>: Interrupt1 edge flag. Set by hardware when an external interrupt edge is detected. It is cleared when interrupt is processed.</div>
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<u>IE0</u>: Interrupt0 edge flag. (Similar to IE1)</div>
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<u>IT1</u>: Interrupt1 type control bit. Set/ cleared by software to specify falling edge / low level triggered external interrupt. </div>
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<u>IT0</u>: Interrupt0 type control bit. (Similar to IT1).</div>
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As mentioned earlier, Timers can operate in four different modes. They are as follows</div>
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<b>Timer Mode-0:</b></div>
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In this mode, the timer is used as a 13-bit UP counter as follows.</div>
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<b><i>Fig 3. Operation of Timer on Mode-0</i></b></div>
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The lower 5 bits of TLX and 8 bits of THX are used for the 13 bit count.Upper 3 bits of TLX are ignored. When the counter rolls over from all 0's to all 1's, TFX flag is set and an interrupt is generated.</div>
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The input pulse is obtained from the previous stage. If TR1/0 bit is 1 and Gate bit is 0, the counter continues counting up. If TR1/0 bit is 1 and Gate bit is 1, then the operation of the counter is controlled by <span style="font-family: Calibri, sans-serif; font-size: 12pt; line-height: 115%;">~</span>INTX input. This mode is useful to measure the width of a given pulse fed to <span style="font-family: Calibri, sans-serif; font-size: 12pt; line-height: 115%;">~</span>INTX input.</div>
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<b>Timer Mode-1:</b></div>
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This mode is similar to mode-0 except for the fact that the Timer operates in 16-bit mode.</div>
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<i><b>Fig 4. Operation of Timer in Mode 1</b></i></div>
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<b>Timer Mode-2: (Auto-Reload Mode)</b></div>
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This is a 8 bit counter/timer operation. Counting is performed in TLX while THX stores a constant value. In this mode when the timer overflows i.e. TLX becomes FFH, it is fed with the value stored in THX. For example if we load THX with 50H then the timer in mode 2 will count from 50H to FFH. After that 50H is again reloaded. This mode is useful in applications like fixed time sampling.</div>
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<b><i>Fig 5. Operation of Timer in Mode 2</i></b></div>
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<b>Timer Mode-3:</b></div>
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Timer 1 in mode-3 simply holds its count. The effect is same as setting TR1=0. Timer0 in mode-3 establishes TL0 and TH0 as two separate counters.</div>
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<b><i>Fig 6. Operation of Timer in Mode 3</i></b></div>
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Control bits TR1 and TF1 are used by Timer-0 (higher 8 bits) (TH0) in Mode-3 while TR0 and TF0 are available to Timer-0 lower 8 bits(TL0).</div>
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Timers / Counters in 8051

Timers / Counters 8051 has two 16-bit programmable UP timers/counters. They can be configured to operate either as timers or as event...

External Memory Access in 8051

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Access to external program memory uses the signal <span style="font-family: Calibri, sans-serif; font-size: 12pt; line-height: 115%; text-align: left;">~</span>PSEN (Program store enable) as the read strobe. Access to external data memory uses <span style="font-family: Calibri, sans-serif; font-size: 12pt; line-height: 115%; text-align: left;">~</span>RD or <span style="font-family: Calibri, sans-serif; font-size: 12pt; line-height: 115%; text-align: left;">~</span>WR (alternate function of P3.7 and P3.6).</div>
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For external program memory, always 16 bit address is used. For example -</div>
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MOVC A, @ A+DPTR</div>
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MOVC A, @ A+PC</div>
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Access to external data memory can be either 8-bit address or 16-bit address -</div>
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8-bit address- MOVX A, @Rp where Rp is either R0 or R1</div>
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MOVX @Rp, A</div>
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16 bit address- MOVX   A,@DPTR</div>
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MOV X  @DPTR, A </div>
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The external memory access in 8051 can be shown by a schematic diagram as given in fig 1.</div>
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<img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEiS4A0hlWftQfxWe-iTDQa13CJyR_YzeOFK7JvEJZKYhXobKNt5RX5FFpVta6n6UUlCSvAo67kMcny4W_UYi7iG8Cy65Q5eS_8zG70vZ45lSIesqWfOw2adVPE-hbqQPOdAhv8H68iJ3ka9/s1600/Schematic+diagram+of+external+memory+access.png" /></div>
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<b><i>Figure 1. Schematic diagram of external memory access</i></b></div>
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If an 8-bit external address is used for data memory (i.e. MOVX @Rp) then the content of Port-2 SFR remains at Port-2 pins throughout the external memory cycle. This facilitates memory paging as the upper 8 bit address remains fixed.</div>
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During any access to external memory, the CPU writes FFH to Port-0 latch (SFR). If the user writes to Port-0 during an external memory fetch, the incoming byte is corrupted.</div>
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External program memory is accessed under the following condition.</div>
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<li>Whenever <span style="font-family: "Calibri","sans-serif"; font-size: 12.0pt; line-height: 115%; mso-ansi-language: EN-US; mso-ascii-theme-font: minor-latin; mso-bidi-font-family: "Times New Roman"; mso-bidi-language: AR-SA; mso-bidi-theme-font: minor-bidi; mso-fareast-font-family: Calibri; mso-fareast-language: EN-US; mso-fareast-theme-font: minor-latin; mso-hansi-theme-font: minor-latin;">~</span>EA is low, or</li>
<li>Whenever PC contains a number higher than 0FFFH (for 8051) or 1FFF (for 8052).</li>
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Some typical use of code/program memory access:</div>
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External program memory can be not only used to store the code, but also for lookup table of various functions required for a particular application. Mathematical functions such as Sine, Square root, Exponential, etc. can be stored in the program memory (Internal or eternal)  and these functions can be accessed using MOVC instruction.</div>
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<img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEh7CvTcfpT9mhWKhNQNPBC-yb7LgXL1Gnx36qOfpgMrLLgzycOCK8I1uE1EeR268NJUuZhxPQN9hfQgpeDVPpsdDbokzJfYa37McEHL0cYDTD3_DLYvfC_MWBYcDW891lfU-9wRj-04KS-d/s1600/Program+memory+showing+the+storage+of+lookup+table.png" /></div>
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<b><i>Figure 2. Program memory showing the storage of lookup table</i></b></div>
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External Memory Access in 8051

Access to external program memory uses the signal ~ PSEN (Program store enable) as the read strobe. Access to external data memory uses ...

Addressing Modes & Port Structure of 8051

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<b>Interfacing External Memory</b></div>
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If external program/data memory are  to be interfaced, they are interfaced in the following way.</div>
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<b><i>Figure 1. Circuit Diagram for Interfacing of External Memory</i></b></div>
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External program memory is fetched if  either of the following two conditions are satisfied.</div>
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<li><span style="font-family: "Calibri","sans-serif"; font-size: 12.0pt; line-height: 115%; mso-ansi-language: EN-US; mso-ascii-theme-font: minor-latin; mso-bidi-font-family: "Times New Roman"; mso-bidi-language: AR-SA; mso-bidi-theme-font: minor-bidi; mso-fareast-font-family: Calibri; mso-fareast-language: EN-US; mso-fareast-theme-font: minor-latin; mso-hansi-theme-font: minor-latin;">~</span>EA (Enable Address) is low.  The microcontroller by default starts searching for program from external program memory.</li>
<li>PC is higher than FFFH for 8051 or 1FFFH for 8052.</li>
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<span style="font-family: Calibri, sans-serif; font-size: 12pt; line-height: 115%;">~</span>PSEN tells the outside world whether the external memory fetched is program memory or data memory. <span style="font-family: Calibri, sans-serif; font-size: 12pt; line-height: 115%;">~</span>EA is user configurable. <span style="font-family: Calibri, sans-serif; font-size: 12pt; line-height: 115%;">~</span>PSEN is processor controlled.</div>
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<b><span style="color: red;">8051 Addressing Modes</span></b></div>
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8051 has four addressing modes.</div>
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<b>1.  Immediate Addressing :</b></div>
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Data is immediately available in the instruction.</div>
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For example -</div>
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ADD A, #77; Adds 77 (decimal) to A and stores in A</div>
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ADD A, #4DH;  Adds 4D (hexadecimal) to A and stores in A</div>
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MOV DPTR, #1000H; Moves 1000 (hexadecimal) to data pointer</div>
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<b>2.  Bank Addressing or Register Addressing :</b></div>
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This way of addressing accesses the bytes in the current register bank. Data is available in the register specified in the instruction. The register bank is decided by 2 bits of Processor Status Word (PSW). </div>
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For example-</div>
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ADD A, R0; Adds content of R0 to A and stores in A</div>
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<b>3. Direct Addressing :</b></div>
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The address of the data is available in the instruction. </div>
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For example -</div>
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MOV A, 088H; Moves content of SFR TCON (address 088H)to A</div>
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<b>4.  Register Indirect Addressing :</b></div>
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The address of data is available in the R0 or R1 registers as specified in the instruction.</div>
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For example -</div>
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MOV A, @R0 moves content of address pointed by R0 to A</div>
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<b>External Data Addressing :</b></div>
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Pointer used for external data addressing can be either R0/R1 (256 byte access) or DPTR (64kbyte access).</div>
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For example -</div>
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MOVX A, @R0; Moves content of 8-bit address pointed by R0 to A</div>
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MOVX A, @DPTR; Moves content of 16-bit address pointed by DPTR to A</div>
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<b>External Code Addressing :</b></div>
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Sometimes we may want to store non-volatile data into the ROM e.g. look-up tables. Such data may require reading the code memory. This may be done as follows -</div>
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MOVC A, @A+DPTR; Moves content of address pointed by A+DPTR to A</div>
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MOVC A, @A+PC; Moves content of address pointed by A+PC to A</div>
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<b><span style="color: red;">I/O Port Configuration</span></b></div>
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Each port of 8051 has bidirectional capability. Port 0 is called 'true bidirectional port' as it floats (tristated) when configured as input. Port-1, 2, 3 are called 'quasi bidirectional port'.</div>
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<b>Port-0  Pin Structure</b></div>
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Port -0 has 8 pins (P0.0-P0.7).</div>
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The structure of a Port-0 pin is shown in fig 2.</div>
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<img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEiNkGEgLKpgIALUEbUKVfsEer4uGMXofbZnWpV7XHZ92fPbPxyo9o2ZmimN279I0anI-EFtZcZ-4fQuPBYJyhh01r0XQzsf3muOJo41U-pY3GLjjgGmk-ifHs2wObZWfzxNG54ptfSTHhe9/s1600/Port-0+Structure.png" /></div>
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<i><b>Figure 2. Port-0 Structure</b></i></div>
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<br /></div>
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Port-0 can be configured as a normal bidirectional I/O port or it can be used for address/data interfacing for accessing external memory. When control is '1', the port is used for address/data interfacing. When the control is '0', the port can be used as a normal bidirectional I/O port.</div>
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<br /></div>
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Let us assume that control is '0'. When the port is used as an input port, '1' is written to the latch. In this situation both the output MOSFETs are 'off'. Hence the output pin floats. This high impedance pin can be pulled up or low by an external source. When the port is used as an output port, a '1' written to the latch again turns 'off' both the output MOSFETs and causes the output pin to float. An external pull-up is required to output a '1'. But when '0' is written to the latch, the pin is pulled down by the lower MOSFET. Hence the output becomes zero.</div>
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<br /></div>
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When the control is '1', address/data bus controls the output driver MOSFETs. If the address/data bus (internal) is '0', the upper MOSFET is 'off' and the lower MOSFET is 'on'. The output becomes '0'. If the address/data bus is '1', the upper transistor is 'on' and the lower transistor is 'off'. Hence the output is '1'. Hence for normal address/data interfacing (for external memory access) no pull-up resistors are required.</div>
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<br /></div>
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Port-0 latch is written to with 1's when used for external memory access.</div>
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<br /></div>
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<b>Port-1  Pin Structure</b></div>
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<br /></div>
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Port-1 has 8 pins (P1.1-P1.7) .The structure of a port-1 pin is shown in fig 3.</div>
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<br /></div>
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<img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEiSYuxdCn7WlftUtnId3kXUaMHv2Spj2u4FUyq7Ysj_u-OTIUm8C7UR1XgGgfki_-7fDwh6eKBQxoA_j2WV6JIpmSj4u3R5NxuMGlVniK8bxPFjG6-HtcSavHTURogPO6pn9HpVW5YcPIjL/s1600/Port+1+Structure.png" /></div>
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<i><b>Figure 3.  Port 1 Structure</b></i></div>
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<br /></div>
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Port-1 does not have any alternate function i.e. it is dedicated solely for I/O interfacing. When used as output port, the pin is pulled up or down through internal pull-up. To use port-1 as input port, '1' has to be written to the latch. In this input mode when '1' is written to the pin by the external device then it read fine. But when '0' is written to the pin by the external device then the external source must sink current due to internal pull-up. If the external device is not able to sink the current the pin voltage may rise, leading to a possible wrong reading.</div>
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<br /></div>
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<b>PORT 2  Pin Structure</b></div>
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<br /></div>
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Port-2 has 8-pins (P2.0-P2.7) . The structure of a port-2 pin is shown in fig 4.</div>
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<br /></div>
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<img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEiDcgx1SmmEbg9fLWdWYLgtkZZSvScr7qu2XGKZN64G_we1w4Pt2f2CUbO4AIlpyJXFdCCsyUzyAGOoWRHCMVsYwpy6fdvtpOEJ7t995gTW8svCcnEHChGy_dZFzVoNgPvFDjzFnraBkP1-/s1600/Port+2+Structure.png" /></div>
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<b><i>Figure 4. Port 2 Structure</i></b></div>
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<br /></div>
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Port-2 is used for higher external address byte or a normal input/output port. The I/O operation is similar to Port-1. Port-2 latch remains stable when Port-2 pin are used for external memory access. Here again due to internal pull-up there is limited current driving capability.</div>
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<br /></div>
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<b>PORT 3 Pin Structure</b></div>
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<br /></div>
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Port-3 has 8 pin (P3.0-P3.7) . Port-3 pins have alternate functions. The structure of a port-3 pin is shown in fig 5.</div>
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<br /></div>
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<img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjgRmAuvTTb-7-lb6Bgb3so7r4y7KTmNIC4_IjEgwW3wpqZoPuPiE69BKy5ZwGvB43k55gYmMOt1BnZYbIwUVPhyphenhyphenUnUVwggXq8Ll4Hou3tKlkBE0W48xItwgj9O6JrroxlMP5qxZKqNQx_I/s1600/Port+3+Structure.png" /></div>
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<i><b>Figure 5. Port 3 Structure</b></i></div>
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Each pin of Port-3 can be individually programmed for I/O operation or for alternate function. The alternate function can be activated only if the corresponding latch has been written to '1'. To use the port as input port, '1' should be written to the latch. This port also has internal pull-up and limited current driving capability.</div>
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Alternate functions of Port-3 pins are -</div>
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<table align="center" border="1" cellpadding="0" cellspacing="0" style="background-color: #e3eaf6; font-family: Arial, Helvetica, sans-serif; height: 204px;"><tbody>
<tr class="BodyText" style="font-size: 12px; text-align: justify;"><td width="60"><div align="center">
P3.0</div>
</td><td width="72"><div align="center">
RxD</div>
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<tr class="BodyText" style="font-size: 12px; text-align: justify;"><td height="22" width="60"><div align="center">
P3.1</div>
</td><td width="72"><div align="center">
TxD</div>
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<tr class="BodyText" style="font-size: 12px; text-align: justify;"><td height="29" width="60"><div align="center">
P3.2</div>
</td><td width="72"><div align="center">
<img height="17" src="http://nptel.ac.in/courses/117104072/micro/lecture6/IMAGES/INTO.gif" width="26" /></div>
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<tr class="BodyText" style="font-size: 12px; text-align: justify;"><td height="30" width="60"><div align="center">
P3.3</div>
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<img height="17" src="http://nptel.ac.in/courses/117104072/micro/lecture6/IMAGES/INT1.gif" width="26" /></div>
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P3.4</div>
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T0</div>
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P3.5</div>
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T1</div>
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<tr class="BodyText" style="font-size: 12px; text-align: justify;"><td height="32" width="60"><div align="center">
P3.6</div>
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<img height="17" src="http://nptel.ac.in/courses/117104072/micro/lecture6/IMAGES/WR.gif" width="20" /></div>
</td></tr>
<tr class="BodyText" style="font-size: 12px; text-align: justify;"><td width="60"><div align="center">
P3.7</div>
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<img height="18" src="http://nptel.ac.in/courses/117104072/micro/lecture6/IMAGES/RD.gif" width="20" /></div>
</td></tr>
</tbody></table>
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<br /></div>
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Note:</div>
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</div>
<ol>
<li>Port 1, 2, 3 each can drive 4 LS TTL inputs.</li>
<li>Port-0 can drive 8 LS TTL inputs in address /data mode. For digital output port, it needs external pull-up resistors.</li>
<li>Ports-1,2and 3 pins can also be driven by open-collector or open-drain outputs.</li>
<li>Each Port 3 bit can be configured either as a normal I/O or as a special function bit.</li>
</ol>
<br />
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<b>Reading a port (port-pins) versus reading a latch</b></div>
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<br /></div>
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There is a subtle difference between reading a latch and reading the output port pin.</div>
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<br /></div>
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The status of the output port pin is sometimes dependant on the connected load. For instance if a port is configured as an output port and a '1' is written to the latch, the output pin should also show '1'. If the output is used to drive the base of a transistor, the transistor turns 'on'.</div>
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<br /></div>
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If the port pin is read, the value will be '0' which is corresponding to the base-emitter voltage of the transistor.</div>
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<br /></div>
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<u><i>Reading a latch</i></u>: Usually the instructions that read the latch, read a value, possibly change it, and then rewrite it to the latch. These are called "read-modify-write" instructions. Examples of a few instructions are-</div>
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ORL P2, A; P2 <-- P2 or A</div>
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MOV P2.1, C; Move carry bit to PX.Y bit.</div>
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In this the latch value of P2 is read, is modified such that P2.1 is the same as Carry and is then written back to P2 latch.</div>
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<br /></div>
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<i><u>Reading a Pin</u></i>: Examples of a few instructions that read port pin, are-</div>
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<br /></div>
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MOV A, P0 ; Move port-0 pin values to A</div>
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<br /></div>
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MOV A, P1; Move port-1 pin values to A</div>
</div>

Addressing Modes & Port Structure of 8051

Interfacing External Memory If external program/data memory are to be interfaced, they are interfaced in the following way. Figur...

Introduction to Intel 8051 Microcontroller

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Some of the microcontrollers of 8051 family are given as follows:</div>
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<strong>DEVICE</strong></div>
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<strong>ON-CHIP DATA MEMORY</strong></div>
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<strong>(bytes)</strong></div>
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<strong>ON-CHIP PROGRAM MEMORY</strong></div>
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<strong>(bytes)</strong></div>
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<strong>16-BIT TIMER/COUNTER</strong></div>
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<strong>NO. OF VECTORED INTERUPTS</strong></div>
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<strong>FULL DUPLEX I/O</strong></div>
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8031</div>
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128</div>
</td><td valign="top" width="124"><div align="center">
None</div>
</td><td valign="top" width="99"><div align="center">
2</div>
</td><td valign="top" width="94"><div align="center">
5</div>
</td><td valign="top" width="88"><div align="center">
1</div>
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8032</div>
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256</div>
</td><td valign="top"><div align="center">
none</div>
</td><td valign="top"><div align="center">
2</div>
</td><td valign="top"><div align="center">
6</div>
</td><td valign="top"><div align="center">
1</div>
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8051</div>
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128</div>
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4k ROM</div>
</td><td valign="top" width="99"><div align="center">
2</div>
</td><td valign="top" width="94"><div align="center">
5</div>
</td><td valign="top" width="88"><div align="center">
1</div>
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8052</div>
</td><td valign="top" width="91"><div align="center">
256</div>
</td><td valign="top" width="124"><div align="center">
8k ROM</div>
</td><td valign="top" width="99"><div align="center">
3</div>
</td><td valign="top" width="94"><div align="center">
6</div>
</td><td valign="top" width="88"><div align="center">
1</div>
</td></tr>
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8751</div>
</td><td valign="top" width="91"><div align="center">
128</div>
</td><td valign="top" width="124"><div align="center">
4k EPROM</div>
</td><td valign="top" width="99"><div align="center">
2</div>
</td><td valign="top" width="94"><div align="center">
5</div>
</td><td valign="top" width="88"><div align="center">
1</div>
</td></tr>
<tr class="BodyText" style="font-size: 12px; text-align: justify;"><td valign="top" width="87"><div align="center">
8752</div>
</td><td valign="top" width="91"><div align="center">
256</div>
</td><td valign="top" width="124"><div align="center">
8k EPROM</div>
</td><td valign="top" width="99"><div align="center">
3</div>
</td><td valign="top" width="94"><div align="center">
6</div>
</td><td valign="top" width="88"><div align="center">
1</div>
</td></tr>
<tr class="BodyText" style="font-size: 12px; text-align: justify;"><td valign="top" width="87"><div align="center">
AT89C51</div>
</td><td valign="top" width="91"><div align="center">
128</div>
</td><td valign="top" width="124"><div align="center">
4k Flash Memory</div>
</td><td valign="top" width="99"><div align="center">
2</div>
</td><td valign="top" width="94"><div align="center">
5</div>
</td><td valign="top" width="88"><div align="center">
1</div>
</td></tr>
<tr class="BodyText" style="font-size: 12px; text-align: justify;"><td valign="top" width="87"><div align="center">
AT89C52</div>
</td><td valign="top" width="91"><div align="center">
256</div>
</td><td valign="top" width="124"><div align="center">
8k Flash memory</div>
</td><td valign="top" width="99"><div align="center">
3</div>
</td><td valign="top" width="94"><div align="center">
6</div>
</td><td valign="top" width="88"><div align="center">
1</div>
</td></tr>
</tbody></table>
</div>
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<br /></div>
<div style="text-align: justify;">
<div>
<b>Basic 8051 Architecture</b></div>
<div>
<br /></div>
<div>
8051 employs Harvard architecture. It has some peripherals such as 32 bit digital I/O, Timers and Serial I/O. The basic architecture of 8051 is given in fig 1.</div>
<div>
<br /></div>
<div class="separator" style="clear: both; text-align: center;">
<img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhR1DrRBcizCvFKERgHT_fdClG8hnJ-f6QoIy92wI6AMZCpi-bCAZHw_cPyahcUcDrgR_2WK-U1y30rhQd1Nc4Clsh3EEgf_jrSfNuIATIPX1n2Zc1cWyXWeys3CEiORBzb3ST6xpnpHDKv/s1600/Drawing1.png" /></div>
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<b><i>Figure 1. Basic 8051 Architecture</i></b></div>
<div>
<div>
<br /></div>
<div>
Various features of 8051 microcontroller are given as follows:</div>
<div>
<ul>
<li>8-bit CPU</li>
<li>16-bit Program Counter</li>
<li>8-bit Processor Status Word (PSW)</li>
<li>8-bit Stack Pointer</li>
<li>Internal RAM of 128bytes</li>
<li>Special Function Registers (SFRs) of 128 bytes</li>
<li>32 I/O pins arranged as four 8-bit ports (P0 - P3)</li>
<li>Two 16-bit timer/counters : T0 and T1</li>
<li>Two external and three internal vectored interrupts</li>
<li>One full duplex serial I/O</li>
</ul>
</div>
</div>
<div>
<div>
<b>8051 Clock and Instruction Cycle</b></div>
<div>
<br /></div>
<div>
In 8051, one instruction cycle consists of twelve (12) clock cycles. Instruction cycle is sometimes called as Machine cycle by some authors.</div>
</div>
<div>
<br /></div>
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<img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjm5tfP5JEnqqjSzfURUOnPQV-RxqazNg1YQtE4KIgCu6NwJy5VX_plUTTKlEZ4IWNxfEHeeN6iMJIhIxVMHWQUTLQTPO2KXKIUFrxw4sWQuLWY-C6oAEK1FaBH1f9zH8r4-OmasgLNHpI7/s1600/instruction+cycle.png" /></div>
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<b><i>Figure 2. Instruction Cycle of 8051</i></b></div>
<div>
<br /></div>
<div>
In 8051, each instruction cycle has six states (S 1 - S 6 ). Each state has two pulses (P1 and P2).</div>
<div>
<br /></div>
<div>
<b>128 bytes of Internal RAM Structure (lower address space)</b></div>
<div>
<br /></div>
<div class="separator" style="clear: both; text-align: center;">
<img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEi6aH8Mr3hGTWXxIc2Zu2lVbgr2jpOUSmxMy9rVD8k32JylKVhx60f43NShWIKutQpwnM1Syix4NsVVdlXHoHWJnKAsNr7HisZ6gzvXmU_mlkMwAbjE4MyxZWs7U8Omo81kD-okJueeAXNd/s1600/ram+structure.png" /></div>
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<b><i>Figure 3. Internal RAM Structure</i></b></div>
<div>
<br /></div>
<div>
The lower 32 bytes are divided into 4 separate banks. Each register bank has 8 registers of one byte each. A register bank is selected depending upon two bank select bits in the PSW register. Next 16 bytes are bit addressable. In total, 128 bits (16X8) are available in bit addressable area. Each bit can be accessed and modified by suitable instructions. The bit addresses are from 00H (LSB of the first byte in 20H) to 7FH (MSB of the last byte in 2FH). Remaining 80bytes of RAM are available for general purpose.</div>
<div>
<br /></div>
<div>
<b>Internal Data Memory and Special Function Register (SFR) Map</b></div>
<div>
<br /></div>
<div class="separator" style="clear: both; text-align: center;">
<img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEidjIuDjuStDhjNCgibV9ukmn3e5GBsSS-v5UYQxXF6Yk-lDegJ9-1uSDKYAJrsCt5Banadx6p0Z1VS_kDO_WPFTMzdB6dBJwE7zISpbCI0o5t3fgwfSZcNieRm1tG3GQk1BC6Lk1UuzJ-f/s1600/data+memory+map.png" /></div>
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<b><i>Figure 4. Internal Data Memory Map</i></b></div>
<div>
<br /></div>
<div>
<div>
The special function registers (SFRs) are mapped in the upper 128 bytes of internal data memory address. Hence there is an address overlap between the upper 128 bytes of data RAM and SFRs. Please note that the upper 128 bytes of data RAM are present only in the 8052 family. The lower 128 bytes of RAM (00H - 7FH) can be accessed both by direct or indirect addressing while the upper 128 bytes of RAM (80H - FFH) are accessed by indirect addressing.The SFRs (80H - FFH) are accessed by direct addressing only. This feature distinguishes the upper 128 bytes of memory from the SFRs, as shown in fig 5.4.</div>
<div>
<br /></div>
<div>
<b>SFR Map</b></div>
<div>
<br /></div>
<div>
The set of Special Function Registers (SFRs) contains important registers such as Accumulator, Register B, I/O Port latch registers, Stack pointer, Data Pointer, Processor Status Word (PSW) and various control registers. Some of these registers are bit addressable (they are marked with a * in the diagram below). The detailed map of various registers is shown in the following figure.</div>
</div>
<div>
<br /></div>
<div>
<table align="center" border="1" cellpadding="1" style="background-color: #e3eaf6; font-family: Arial, Helvetica, sans-serif; width: 549px;"><tbody>
<tr class="BodyText" style="font-size: 12px; text-align: justify;"><td width="42">F8H</td><td width="54"></td><td width="55"></td><td width="60"></td><td width="61"></td><td width="57"></td><td width="57"></td><td width="53"></td><td width="52"></td></tr>
<tr class="BodyText" style="font-size: 12px; text-align: justify;"><td>F0H</td><td>B*</td><td></td><td></td><td></td><td></td><td></td><td></td><td></td></tr>
<tr class="BodyText" style="font-size: 12px; text-align: justify;"><td>E8H</td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td></tr>
<tr class="BodyText" style="font-size: 12px; text-align: justify;"><td>E0H</td><td>ACC*</td><td></td><td></td><td></td><td></td><td></td><td></td><td></td></tr>
<tr class="BodyText" style="font-size: 12px; text-align: justify;"><td>D8H</td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td></tr>
<tr class="BodyText" style="font-size: 12px; text-align: justify;"><td>D0H</td><td>PSW*</td><td></td><td></td><td></td><td></td><td></td><td></td><td></td></tr>
<tr class="BodyText" style="font-size: 12px; text-align: justify;"><td>C8H</td><td>(T2CON)*</td><td></td><td>(RCAP2L)</td><td>(RCAP2H)</td><td>(TL2)</td><td>(TH2)</td><td></td><td></td></tr>
<tr class="BodyText" style="font-size: 12px; text-align: justify;"><td>C0H</td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td></tr>
<tr class="BodyText" style="font-size: 12px; text-align: justify;"><td>B8H</td><td>IP*</td><td></td><td></td><td></td><td></td><td></td><td></td><td></td></tr>
<tr class="BodyText" style="font-size: 12px; text-align: justify;"><td>B0H</td><td>P3*</td><td></td><td></td><td></td><td></td><td></td><td></td><td></td></tr>
<tr class="BodyText" style="font-size: 12px; text-align: justify;"><td>A8H</td><td>IE*</td><td></td><td></td><td></td><td></td><td></td><td></td><td></td></tr>
<tr class="BodyText" style="font-size: 12px; text-align: justify;"><td>A0H</td><td>P2*</td><td></td><td></td><td></td><td></td><td></td><td></td><td></td></tr>
<tr class="BodyText" style="font-size: 12px; text-align: justify;"><td>98H</td><td>SCON*</td><td>SBUF</td><td></td><td></td><td></td><td></td><td></td><td></td></tr>
<tr class="BodyText" style="font-size: 12px; text-align: justify;"><td>90H</td><td>P1*</td><td></td><td></td><td></td><td></td><td></td><td></td><td></td></tr>
<tr class="BodyText" style="font-size: 12px; text-align: justify;"><td>88H</td><td>TCON*</td><td>TMOD</td><td>TL0</td><td>TL1</td><td>TH0</td><td>TH1</td><td></td><td></td></tr>
<tr class="BodyText" style="font-size: 12px; text-align: justify;"><td>80H</td><td>P0*</td><td>SP</td><td>DPL</td><td>DPH</td><td></td><td></td><td></td><td>PCON</td></tr>
</tbody></table>
<div style="text-align: center;">
<i><b>Figure 5. SFR Map</b></i></div>
</div>
<div>
<br /></div>
<div>
<div>
It should be noted hat all registers appearing in the first column are bit addressable. The bit address of a bit in the register is calculated as follows.</div>
<div>
Bit address of 'b' bit of register 'R' is</div>
<div>
                       Address of register 'R' + b</div>
<div>
                       where  0   ≤  b ≤ 7</div>
</div>
<div>
<br /></div>
<div>
<b>Processor Status Word (PSW)     Address=D0H</b></div>
<div>
<br /></div>
<div class="separator" style="clear: both; text-align: center;">
<img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgIpRrFGpxEetTe_XWUlAmj52EGpAqKis5m9ZuBcJBx8xEO6Ixt1Oo1VsY5Te7ObLzDSXlqUuEv5KAC3AgHPgZZ5yX7EaMisTqhm7IcOK27uOnHH1dGazaLlVLkT9c07yRR9P_lKTK702rD/s1600/processor+status+word.png" /></div>
<div class="separator" style="clear: both; text-align: center;">
<b><i>Figure 6. Processor Status Word</i></b></div>
<div>
<br /></div>
<div>
PSW register stores the important status conditions of the microcontroller. It also stores the bank select bits (RS1 & RS0) for register bank selection.</div>
</div>
</div>

Introduction to Intel 8051 Microcontroller

Some of the microcontrollers of 8051 family are given as follows: DEVICE ON-CHIP DATA MEMORY (bytes) ON-CHIP PROGRAM MEMORY ...

Introduction to Microcontrollers & Microprocessors

<div dir="ltr" style="text-align: left;" trbidi="on">
<div style="text-align: justify;">
<span style="font-family: inherit;"><b>What is a Microcontroller? </b>

A Microcontroller is a
 programmable digital processor with necessary peripherals. Both 
microcontrollers and microprocessors are complex sequential digital 
circuits meant to carry out job according to the program / instructions.
 Sometimes analog input/output interface makes a part of microcontroller
 circuit of mixed mode(both analog and digital nature).</span></div>
<div style="text-align: justify;">
<div class="separator" style="clear: both; text-align: center;">
<img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjGmME3jQ6t0LewcVyFnUxa8foIFsrr1__wrIMq9mG_0Ygcsk6gBg1dRmaTWqLhhM5la_-YdGm3nYVFZW5SyxH2foZ8Syb73FEYDdpdID0oPtcxRuAqfAEKaV0j0H1JVsRAGCisbw7_eWrs/s1600/intel_8051.png" /></div>
<div class="separator" style="clear: both; text-align: center;">
</div>
<br /></div>
<div class="SubHeading" style="text-align: justify;">
<span style="font-family: inherit;"><b>Microcontrollers Vs Microprocessors </b></span></div>
<div style="text-align: justify;">
<span style="font-family: inherit;">
            
            
              </span></div>
<ol style="text-align: justify;">
<li><span style="font-family: inherit;">A microprocessor requires an external memory for 
program/data storage. Instruction execution requires movement of data 
from the external memory to the microprocessor or vice versa. Usually, 
microprocessors have good computing power and they have higher clock 
speed to facilitate faster computation. </span></li>
<li><span style="font-family: inherit;">A microcontroller has required on-chip memory with 
associated peripherals. A microcontroller can be thought of a 
microprocessor with inbuilt peripherals. </span></li>
<li><span style="font-family: inherit;">A microcontroller does not require much additional 
interfacing ICs for operation and it functions as a stand alone system. 
The operation of a microcontroller is multipurpose, just like a Swiss 
knife. </span></li>
<li><span style="font-family: inherit;">Microcontrollers are also called embedded 
controllers. A microcontroller clock speed is limited only to a few tens
 of MHz. Microcontrollers are numerous and many of them are application 
specific. </span></li>
</ol>
<div style="text-align: justify;">
<span style="font-family: inherit;"></span><b class="SubHeading">Development/Classification of microcontrollers (Invisible) </b> 
            
            
              </div>
<div style="text-align: justify;">
Microcontrollers have 
gone through a silent evolution (invisible). The evolution can be 
rightly termed as silent as the impact or application of a 
microcontroller is not well known to a common user, although 
microcontroller technology has undergone significant change since early 
1970's. Development of some popular microcontrollers is given as 
follows.</div>
<div style="text-align: justify;">
<br /></div>
<table align="center" border="1" cellpadding="1" cellspacing="0"><tbody>
<tr class="BodyText"><td width="187">Intel 4004 </td>
                  <td width="264">4 bit (2300 PMOS trans, 108 kHz) </td>
                  <td width="54">1971 </td>
                </tr>
<tr class="BodyText">
                  <td width="187">Intel 8048 </td>
                  <td width="264">8 bit </td>
                  <td width="54">1976</td>
                </tr>
<tr class="BodyText">
                  <td width="187">Intel 8031 </td>
                  <td width="264">8 bit (ROM-less) </td>
                  <td width="54">.</td>
                </tr>
<tr class="BodyText">
                  <td width="187">Intel 8051 </td>
                  <td width="264">8 bit (Mask ROM) </td>
                  <td width="54">1980</td>
                </tr>
<tr class="BodyText">
                  <td width="187">Microchip PIC16C64 </td>
                  <td width="264">8 bit </td>
                  <td width="54">1985 </td>
                </tr>
<tr class="BodyText">
                  <td width="187">Motorola 68HC11 </td>
                  <td width="264">8 bit (on chip ADC) </td>
                  <td width="54">.</td>
                </tr>
<tr class="BodyText">
                  <td width="187">Intel 80C196 </td>
                  <td width="264">16 bit </td>
                  <td width="54">1982</td>
                </tr>
<tr class="BodyText">
                  <td width="187">Atmel AT89C51 </td>
                  <td width="264">8 bit (Flash memory) </td>
                  <td width="54">.</td>
                </tr>
<tr class="BodyText">
                  <td width="187">Microchip PIC 16F877 </td>
                  <td width="264">8 bit (Flash memory + ADC) </td>
                  <td class="BodyText" width="54">.</td></tr>
</tbody></table>
<div style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
<b>Development of microprocessors (Visible)</b><br />
Microprocessors have 
undergone significant evolution over the past four decades. This 
development is clearly perceptible to a common user, especially, in 
terms of phenomenal growth in capabilities of personal computers. 
Development of some of the microprocessors can be given as follows.<br />
<br /></div>
<div style="text-align: justify;">
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</div>
</div>

Introduction to Microcontrollers & Microprocessors

What is a Microcontroller? A Microcontroller is a programmable digital processor with necessar...

ECEstream

8051 Sample Assembly Language Programs

Serial Communication in 8051

Program Branching Instructions in 8051

Interrupts in 8051

Timers / Counters in 8051

External Memory Access in 8051

Addressing Modes & Port Structure of 8051

Introduction to Intel 8051 Microcontroller

Introduction to Microcontrollers & Microprocessors

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